]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
imx: imx8mp_rsb3720a1: convert to DM_SERIAL
authorPeng Fan <peng.fan@nxp.com>
Thu, 5 May 2022 07:43:28 +0000 (15:43 +0800)
committerStefano Babic <sbabic@denx.de>
Fri, 20 May 2022 10:36:48 +0000 (12:36 +0200)
Enable CONFIG_DM_SERIAL. uart2 and its pinmux was already
marked with u-boot,dm-spl.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c
configs/imx8mp_rsb3720a1_4G_defconfig
configs/imx8mp_rsb3720a1_6G_defconfig
include/configs/imx8mp_rsb3720.h

index 782025dc785685e0e6de8e56c4ba9a16e490eb0d..f129ebd429bdb6191624e418f29c3bc8d3a9c04e 100644 (file)
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
 #define WDOG_PAD_CTRL  (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
 
-static const iomux_v3_cfg_t uart_pads[] = {
-       MX8MP_PAD_ECSPI1_SCLK__UART3_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
-       MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
 static const iomux_v3_cfg_t wdog_pads[] = {
        MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
 };
@@ -81,8 +75,6 @@ int board_early_init_f(void)
 
        set_wdog_reset(wdog);
 
-       imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
-
        init_uart_clk(2);
 
        return 0;
index d7f1aa0f1550314e8477df44679d37b6a5cf54c6..323a7eacdcab9679a3b1db700df7c94b726176e8 100644 (file)
@@ -133,6 +133,7 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_S35392A=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
index 7ceac2b14e3af6d1cf8d348ab38193eb73ebb94c..3feb6396d5f6587d6fd0bf36a4377fdce93fa3e7 100644 (file)
@@ -134,6 +134,7 @@ CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_SPL_DM_REGULATOR_GPIO=y
 CONFIG_DM_RTC=y
 CONFIG_RTC_S35392A=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
index cd8116f6c932141e2a65444ca9d7d823377b67fa..52e8ea8f86af606dfba023447661cfcf03d202f2 100644 (file)
 #define PHYS_SDRAM_2_SIZE              0x80000000      /* 2 GB */
 #endif
 
-#define CONFIG_MXC_UART_BASE           UART_BASE_ADDR(3)
-
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE              2048
 #define CONFIG_SYS_MAXARGS             64