MSCC: add board support for the Luton based evaluation board

Adding the support for the Luton boards PCB91 which share common code with
the Ocelots boards, including board code, device tree and configuration.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

diff --git a/MAINTAINERS b/MAINTAINERS
index d9de9153aa5f0491bcb3ad044ae47c796959578e..bb0a107db5be1bb15c74c27e1738b9f1442cbbaf 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -518,6 +518,7 @@ M:  Lars Povlsen <lars.povlsen@microchip.com>
 M:     Horatiu Vultur <horatiu.vultur@microchip.com>
 S:     Maintained
 F:     arch/mips/mach-mscc/
+F:     arch/mips/dts/luton*
 F:     arch/mips/dts/mscc*
 F:     arch/mips/dts/ocelot*
 F:     board/mscc/

diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
new file mode 100644 (file)
index 0000000..74f9274
--- /dev/null
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,luton.dtsi"
+
+/ {
+       model = "Luton10 PCB091 Reference Board";
+       compatible = "mscc,luton-pcb091", "mscc,luton";
+
+       aliases {
+               serial0 = &uart0;
+               spi0 = &spi0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&spi0 {
+       status = "okay";
+       spi-flash@0 {
+               compatible = "spi-flash";
+               spi-max-frequency = <18000000>; /* input clock */
+               reg = <0>; /* CS0 */
+               spi-cs-high;
+       };
+};
+

diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
new file mode 100644 (file)
index 0000000..6a4ad2a
--- /dev/null
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       #address-cells = <1>;
+       #size-cells = <1>;
+       compatible = "mscc,luton";
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       compatible = "mips,mips24KEc";
+                       device_type = "cpu";
+                       reg = <0>;
+               };
+       };
+
+       aliases {
+               serial0 = &uart0;
+       };
+
+       ahb_clk: ahb-clk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <208333333>;
+       };
+
+       ahb {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0x60000000 0x10200000>;
+
+               uart0: serial@10100000 {
+                       pinctrl-0 = <&uart_pins>;
+                       pinctrl-names = "default";
+
+                       compatible = "ns16550a";
+                       reg = <0x10100000 0x20>;
+                       clocks = <&ahb_clk>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+
+                       status = "disabled";
+               };
+
+               gpio: pinctrl@70068 {
+                       compatible = "mscc,luton-pinctrl";
+                       reg = <0x70068 0x68>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&gpio 0 0 32>;
+
+                       uart_pins: uart-pins {
+                               pins = "GPIO_30", "GPIO_31";
+                               function = "uart";
+                       };
+
+               };
+
+               gpio_spi_bitbang: gpio@10000064 {
+                       compatible = "mscc,spi-bitbang-gpio";
+                       reg = <0x10000064 0x4>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+               };
+
+               spi0: spi-bitbang {
+                       compatible = "spi-gpio";
+                       status = "okay";
+                       gpio-sck = <&gpio_spi_bitbang 6 0>;
+                       gpio-miso = <&gpio_spi_bitbang 0 0>;
+                       gpio-mosi = <&gpio_spi_bitbang 5 0>;
+                       cs-gpios = <&gpio_spi_bitbang 1 0>;
+                       num-chipselects = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
+};

diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index fc806fc1f3519f88b4e928cc0fb528047c73d58f..0e35b77c9db9c24a2bd9a39ef2f601ee35da76b4 100644 (file)
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -81,4 +81,6 @@ endchoice
 
 source "board/mscc/ocelot/Kconfig"
 
+source "board/mscc/luton/Kconfig"
+
 endmenu

diff --git a/board/mscc/luton/Kconfig b/board/mscc/luton/Kconfig
new file mode 100644 (file)
index 0000000..e119980
--- /dev/null
+++ b/board/mscc/luton/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+if SOC_LUTON
+
+config SYS_VENDOR
+       default "mscc"
+
+config SYS_BOARD
+       default "luton"
+
+config SYS_CONFIG_NAME
+       default "luton"
+
+endif

diff --git a/board/mscc/luton/Makefile b/board/mscc/luton/Makefile
new file mode 100644 (file)
index 0000000..b27f7c7
--- /dev/null
+++ b/board/mscc/luton/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_LUTON)        := luton.o

diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
new file mode 100644 (file)
index 0000000..41fc6d5
--- /dev/null
+++ b/board/mscc/luton/luton.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MSCC_GPIO_ALT0         0x88
+#define MSCC_GPIO_ALT1         0x8C
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_debug_uart_init(void)
+{
+       /* too early for the pinctrl driver, so configure the UART pins here */
+       setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(30) | BIT(31));
+}
+
+int board_early_init_r(void)
+{
+       /* Prepare SPI controller to be used in master mode */
+       writel(0, BASE_CFG + ICPU_SW_MODE);
+
+       /* Address of boot parameters */
+       gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+       return 0;
+}

diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig
new file mode 100644 (file)
index 0000000..d7476c4
--- /dev/null
+++ b/configs/mscc_luton_defconfig
@@ -0,0 +1,64 @@
+CONFIG_MIPS=y
+CONFIG_SYS_TEXT_BASE=0x40000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0x70100000
+CONFIG_DEBUG_UART_CLOCK=208333333
+CONFIG_ARCH_MSCC=y
+CONFIG_TARGET_LUTON_PCB091=y
+CONFIG_DDRTYPE_MT47H128M8HQ=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_MIPS_BOOT_FDT=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200"
+CONFIG_LOGLEVEL=7
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_SYS_PROMPT="pcb091 # "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_DHCP=y
+# CONFIG_NET_TFTP_VARS is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)"
+# CONFIG_ISO_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SOFT_SPI=y
+CONFIG_LZMA=y