armv8/cache: Consolidate setting for MAIR and TCR

Move setting for MAIR and TCR to cache_v8.c, to avoid conflict with
sub-architecture.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 131fdaba3f38261932c1de2ecf3d8faa5a1e8d41..7acae1b0aca55639f3271fa46f445816e2951b87 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -45,15 +45,31 @@ static void mmu_setup(void)
 
        /* load TTBR0 */
        el = current_el();
-       if (el == 1)
+       if (el == 1) {
                asm volatile("msr ttbr0_el1, %0"
                             : : "r" (gd->arch.tlb_addr) : "memory");
-       else if (el == 2)
+               asm volatile("msr tcr_el1, %0"
+                            : : "r" (TCR_FLAGS | TCR_EL1_IPS_BITS)
+                            : "memory");
+               asm volatile("msr mair_el1, %0"
+                            : : "r" (MEMORY_ATTRIBUTES) : "memory");
+       } else if (el == 2) {
                asm volatile("msr ttbr0_el2, %0"
                             : : "r" (gd->arch.tlb_addr) : "memory");
-       else
+               asm volatile("msr tcr_el2, %0"
+                            : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
+                            : "memory");
+               asm volatile("msr mair_el2, %0"
+                            : : "r" (MEMORY_ATTRIBUTES) : "memory");
+       } else {
                asm volatile("msr ttbr0_el3, %0"
                             : : "r" (gd->arch.tlb_addr) : "memory");
+               asm volatile("msr tcr_el3, %0"
+                            : : "r" (TCR_FLAGS | TCR_EL2_IPS_BITS)
+                            : "memory");
+               asm volatile("msr mair_el3, %0"
+                            : : "r" (MEMORY_ATTRIBUTES) : "memory");
+       }
 
        /* enable the mmu */
        set_sctlr(get_sctlr() | CR_M);

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index bcc26030983edfde9ebdefb9b0990c8da3470718..90daa4d2fd8cd3f2e1b14fd96cca8d414e4df0e0 100644 (file)
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -128,28 +128,6 @@ ENTRY(c_runtime_cpu_setup)
        isb     sy
 #endif
 
-#ifndef CONFIG_SYS_DCACHE_OFF
-       /*
-        * Setup MAIR and TCR.
-        */
-       ldr     x0, =MEMORY_ATTRIBUTES
-       ldr     x1, =TCR_FLAGS
-
-       switch_el x2, 3f, 2f, 1f
-3:     orr     x1, x1, TCR_EL3_IPS_BITS
-       msr     mair_el3, x0
-       msr     tcr_el3, x1
-       b       0f
-2:     orr     x1, x1, TCR_EL2_IPS_BITS
-       msr     mair_el2, x0
-       msr     tcr_el2, x1
-       b       0f
-1:     orr     x1, x1, TCR_EL1_IPS_BITS
-       msr     mair_el1, x0
-       msr     tcr_el1, x1
-0:
-#endif
-
        /* Relocate vBAR */
        adr     x0, vectors
        switch_el x1, 3f, 2f, 1f