soc {
dsi: dsi@40016c00 {
compatible = "st,stm32-dsi";
- reg = <0x40016C00 0x800>;
+ reg = <0x40016c00 0x800>;
resets = <&rcc STM32F7_APB2_RESET(DSI)>;
- clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
+ clocks = <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
<&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
<&clk_hse>;
clock-names = "pclk", "px_clk", "ref";
};
&qspi {
- reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
+ reg = <0xa0001000 0x1000>, <0x90000000 0x4000000>;
flash0: mx66l51235l@0 {
#address-cells = <1>;
#size-cells = <1>;