microblaze: cache: improve dcache Kconfig options

Replace CONFIG_DCACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports
the "wdc" (Write to Data Cache) instruction. It will be used to guard
"wdc" invocations in microblaze cache code.

Also, drop all ifdefs around flush_cache() calls and only keep one
CONFIG_IS_ENABLED() guard within flush_cache() itself.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-5-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 6f45d19330a1363839609d067b3d8b8048d52148..11ccbcc9f205290fb647cf20c3ed50e6af97655a 100644 (file)
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -39,10 +39,6 @@ config TARGET_MICROBLAZE_GENERIC
 
 endchoice
 
-config DCACHE
-       bool "Enable dcache support"
-       default y
-
 config ICACHE
        bool "Enable icache support"
        default y

diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index b6126de1944d693d2385c6eb60746585ec1a7eb1..4e8e228a22ceb35a0f9f332f88838c1b8198f5ae 100644 (file)
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -49,26 +49,31 @@ void dcache_enable(void)
 
 void dcache_disable(void)
 {
-#ifdef CONFIG_DCACHE
        flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#endif
+
        MSRCLR(0x80);
 }
 
 void flush_cache(ulong addr, ulong size)
 {
        int i;
-       for (i = 0; i < size; i += 4)
+       for (i = 0; i < size; i += 4) {
                asm volatile (
 #ifdef CONFIG_ICACHE
                                "wic    %0, r0;"
 #endif
                                "nop;"
-#ifdef CONFIG_DCACHE
+                               :
+                               : "r" (addr + i)
+                               : "memory");
+
+               if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) {
+                       asm volatile (
                                "wdc.flush      %0, r0;"
-#endif
                                "nop;"
                                :
                                : "r" (addr + i)
                                : "memory");
+               }
+       }
 }

diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index b652d2767a2c827b0931833d97184457842f5c54..dba6226ce56654b6d925eebb6b920169aeaaf035 100644 (file)
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -57,9 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
               "(fake run for tracing)" : "");
        bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
 
-#ifdef CONFIG_DCACHE
        flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#endif
 
        if (!fake) {
                /*

diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig
index 117b476f3f4133487f87c1748cf1d963bbf5be7d..b00ce6f59a48b8b73f2b6bee507bce659e190746 100644 (file)
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -63,4 +63,15 @@ config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
          Memory address location of the exception vector table. It is
          configurable via the C_BASE_VECTORS hdl parameter.
 
+config XILINX_MICROBLAZE0_USE_WDC
+       bool "MicroBlaze wdc instruction support"
+       default y
+       help
+         Enable this option if the MicroBlaze processor is configured with
+         support for the "wdc" (Write to Data Cache) instruction.
+
+config SPL_XILINX_MICROBLAZE0_USE_WDC
+       bool
+       default XILINX_MICROBLAZE0_USE_WDC
+
 endif