clk: renesas: Synchronize RZ R8A774A1 RZ/G2M clock tables with Linux 6.6.3

Synchronize RZ R8A774A1 RZ/G2M clock tables with Linux 6.6.3,
commit bd3a9e5771a8b332f466d06f7c130a69cab0d526 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 6280061af891ee983863328eef67f83e021ec2fa..6f94906cc994d64c18b3868428cddf40a547ab33 100644 (file)
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -75,6 +75,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
        /* Core Clock Outputs */
        DEF_GEN3_Z("z",         R8A774A1_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
        DEF_GEN3_Z("z2",        R8A774A1_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),
+       DEF_GEN3_Z("zg",        R8A774A1_CLK_ZG,    CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24),
        DEF_FIXED("ztr",        R8A774A1_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED("ztrd2",      R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
        DEF_FIXED("zt",         R8A774A1_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -122,6 +123,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
+       DEF_MOD("3dge",                  112,   R8A774A1_CLK_ZG),
        DEF_MOD("tmu4",                  121,   R8A774A1_CLK_S0D6),
        DEF_MOD("tmu3",                  122,   R8A774A1_CLK_S3D2),
        DEF_MOD("tmu2",                  123,   R8A774A1_CLK_S3D2),
@@ -212,6 +214,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
        DEF_MOD("rpc-if",                917,   R8A774A1_CLK_RPCD2),
        DEF_MOD("i2c6",                  918,   R8A774A1_CLK_S0D6),
        DEF_MOD("i2c5",                  919,   R8A774A1_CLK_S0D6),
+       DEF_MOD("adg",                   922,   R8A774A1_CLK_S0D4),
        DEF_MOD("iic-pmic",              926,   R8A774A1_CLK_CP),
        DEF_MOD("i2c4",                  927,   R8A774A1_CLK_S0D6),
        DEF_MOD("i2c3",                  928,   R8A774A1_CLK_S0D6),