arm64: dts: rockchip: add USBDP phys on rk3588

Add both USB3-DisplayPort PHYs to RK3588 SoC DT.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: e18e5e8188f2671abf63abe7db5f21555705130f ]

(cherry picked from commit 5110caca9865718616cf7093ed4a9a1bc54780db)
Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
index 5519c1430cb7a92df91765243ac29fc7e1a2407b..4fdd047c9eb9869b5f753508f2a557d0bec7b986 100644 (file)
--- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
@@ -17,6 +17,36 @@
                reg = <0x0 0xfd5c0000 0x0 0x100>;
        };
 
+       usbdpphy1_grf: syscon@fd5cc000 {
+               compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+               reg = <0x0 0xfd5cc000 0x0 0x4000>;
+       };
+
+       usb2phy1_grf: syscon@fd5d4000 {
+               compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
+               reg = <0x0 0xfd5d4000 0x0 0x4000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               u2phy1: usb2phy@4000 {
+                       compatible = "rockchip,rk3588-usb2phy";
+                       reg = <0x4000 0x10>;
+                       #clock-cells = <0>;
+                       clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+                       clock-names = "phyclk";
+                       clock-output-names = "usb480m_phy1";
+                       interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
+                       resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
+                       reset-names = "phy", "apb";
+                       status = "disabled";
+
+                       u2phy1_otg: otg-port {
+                               #phy-cells = <0>;
+                               status = "disabled";
+                       };
+               };
+       };
+
        i2s8_8ch: i2s@fddc8000 {
                compatible = "rockchip,rk3588-i2s-tdm";
                reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -310,6 +340,28 @@
                };
        };
 
+       usbdp_phy1: phy@fed90000 {
+               compatible = "rockchip,rk3588-usbdp-phy";
+               reg = <0x0 0xfed90000 0x0 0x10000>;
+               #phy-cells = <1>;
+               clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+                        <&cru CLK_USBDP_PHY1_IMMORTAL>,
+                        <&cru PCLK_USBDPPHY1>,
+                        <&u2phy1>;
+               clock-names = "refclk", "immortal", "pclk", "utmi";
+               resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
+                        <&cru SRST_USBDP_COMBO_PHY1_CMN>,
+                        <&cru SRST_USBDP_COMBO_PHY1_LANE>,
+                        <&cru SRST_USBDP_COMBO_PHY1_PCS>,
+                        <&cru SRST_P_USBDPPHY1>;
+               reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+               rockchip,u2phy-grf = <&usb2phy1_grf>;
+               rockchip,usb-grf = <&usb_grf>;
+               rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
+               rockchip,vo-grf = <&vo0_grf>;
+               status = "disabled";
+       };
+
        combphy1_ps: phy@fee10000 {
                compatible = "rockchip,rk3588-naneng-combphy";
                reg = <0x0 0xfee10000 0x0 0x100>;

diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 58d12969b7ee09ece02b33c7bf2925ec58e351c4..9063c0bb0f02ba727fe6e34ffeacfd5e55e935ce 100644 (file)
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -572,12 +572,23 @@
                reg = <0x0 0xfd5a4000 0x0 0x2000>;
        };
 
+       vo0_grf: syscon@fd5a6000 {
+               compatible = "rockchip,rk3588-vo-grf", "syscon";
+               reg = <0x0 0xfd5a6000 0x0 0x2000>;
+               clocks = <&cru PCLK_VO0GRF>;
+       };
+
        vo1_grf: syscon@fd5a8000 {
                compatible = "rockchip,rk3588-vo-grf", "syscon";
                reg = <0x0 0xfd5a8000 0x0 0x100>;
                clocks = <&cru PCLK_VO1GRF>;
        };
 
+       usb_grf: syscon@fd5ac000 {
+               compatible = "rockchip,rk3588-usb-grf", "syscon";
+               reg = <0x0 0xfd5ac000 0x0 0x4000>;
+       };
+
        php_grf: syscon@fd5b0000 {
                compatible = "rockchip,rk3588-php-grf", "syscon";
                reg = <0x0 0xfd5b0000 0x0 0x1000>;
@@ -593,6 +604,36 @@
                reg = <0x0 0xfd5c4000 0x0 0x100>;
        };
 
+       usbdpphy0_grf: syscon@fd5c8000 {
+               compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+               reg = <0x0 0xfd5c8000 0x0 0x4000>;
+       };
+
+       usb2phy0_grf: syscon@fd5d0000 {
+               compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
+               reg = <0x0 0xfd5d0000 0x0 0x4000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               u2phy0: usb2phy@0 {
+                       compatible = "rockchip,rk3588-usb2phy";
+                       reg = <0x0 0x10>;
+                       #clock-cells = <0>;
+                       clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
+                       clock-names = "phyclk";
+                       clock-output-names = "usb480m_phy0";
+                       interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
+                       resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
+                       reset-names = "phy", "apb";
+                       status = "disabled";
+
+                       u2phy0_otg: otg-port {
+                               #phy-cells = <0>;
+                               status = "disabled";
+                       };
+               };
+       };
+
        usb2phy2_grf: syscon@fd5d8000 {
                compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
                reg = <0x0 0xfd5d8000 0x0 0x4000>;
@@ -2449,6 +2490,28 @@
                status = "disabled";
        };
 
+       usbdp_phy0: phy@fed80000 {
+               compatible = "rockchip,rk3588-usbdp-phy";
+               reg = <0x0 0xfed80000 0x0 0x10000>;
+               #phy-cells = <1>;
+               clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
+                        <&cru CLK_USBDP_PHY0_IMMORTAL>,
+                        <&cru PCLK_USBDPPHY0>,
+                        <&u2phy0>;
+               clock-names = "refclk", "immortal", "pclk", "utmi";
+               resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
+                        <&cru SRST_USBDP_COMBO_PHY0_CMN>,
+                        <&cru SRST_USBDP_COMBO_PHY0_LANE>,
+                        <&cru SRST_USBDP_COMBO_PHY0_PCS>,
+                        <&cru SRST_P_USBDPPHY0>;
+               reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+               rockchip,u2phy-grf = <&usb2phy0_grf>;
+               rockchip,usb-grf = <&usb_grf>;
+               rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
+               rockchip,vo-grf = <&vo0_grf>;
+               status = "disabled";
+       };
+
        combphy0_ps: phy@fee00000 {
                compatible = "rockchip,rk3588-naneng-combphy";
                reg = <0x0 0xfee00000 0x0 0x100>;