t210: do not enable PLLE and UPHY PLL HW PWRSEQ

This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.

Adds call to board_cleanup_before_linux to facilitate this.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index 2467e0b87be230b5077596ed4e28bb148b3385b3..35752037bcf1f825460d1fa5c53bb47758d38cf9 100644 (file)
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -32,6 +32,8 @@ void sdelay(unsigned long loops)
                          "b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
 }
 
+void __weak board_cleanup_before_linux(void){}
+
 int cleanup_before_linux(void)
 {
        /*
@@ -40,6 +42,9 @@ int cleanup_before_linux(void)
         *
         * disable interrupt and turn off caches etc ...
         */
+
+       board_cleanup_before_linux();
+
        disable_interrupts();
 
        /*

diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
index deccdf455d9b195724cec6287ac419dd18ddd296..7e14d8109d11337a35b69e3bc45bb78aba949ebb 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h
+++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h
@@ -16,6 +16,7 @@ struct tegra_xusb_phy;
 struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
 
 void tegra_xusb_padctl_init(void);
+void tegra_xusb_padctl_exit(void);
 int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
 int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
 int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);

diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c
index d3497a2673e5588faf624df0bf04fdc43cf755d2..787ff974203605ec117d54560869117fb02e090c 100644 (file)
--- a/arch/arm/mach-tegra/board2.c
+++ b/arch/arm/mach-tegra/board2.c
@@ -181,6 +181,12 @@ int board_init(void)
        return nvidia_board_init();
 }
 
+void board_cleanup_before_linux(void)
+{
+       /* power down UPHY PLL */
+       tegra_xusb_padctl_exit();
+}
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 static void __gpio_early_init(void)
 {

diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index b240860f08cf30e8c74dbdcf0f16dd701dc1978b..f1b25e262a1f60f2654d370a2af94f5021c2d75d 100644 (file)
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -1235,25 +1235,6 @@ int tegra_plle_enable(void)
        value &= ~PLLE_SS_CNTL_INTERP_RESET;
        writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
 
-       /* 7. Enable HW power sequencer for PLLE */
-
-       value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
-       value &= ~PLLE_MISC_IDDQ_SWCTL;
-       writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
-
-       value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
-       value &= ~PLLE_AUX_SS_SWCTL;
-       value &= ~PLLE_AUX_ENABLE_SWCTL;
-       value |= PLLE_AUX_SS_SEQ_INCLUDE;
-       value |= PLLE_AUX_USE_LOCKDET;
-       writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
-       /* 8. Wait 1 us */
-
-       udelay(1);
-       value |= PLLE_AUX_SEQ_ENABLE;
-       writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
-
        return 0;
 }
 

diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index ab6684f027c72890f03175daf32cec80654e020d..64dc297ae27b31dbb75fe7c943a7b6dd1e0e0dd2 100644 (file)
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -170,6 +170,17 @@ static int phy_unprepare(struct tegra_xusb_phy *phy)
        return tegra_xusb_padctl_disable(phy->padctl);
 }
 
+#define XUSB_PADCTL_USB3_PAD_MUX 0x28
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
+#define  XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
+
 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
 #define  XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
@@ -366,31 +377,6 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
        value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
        padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 
-       value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-       value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
-       value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
-       value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
-       value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
-       writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-
-       value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
-       value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
-       padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
-
-       value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
-       value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
-       padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
-
-       value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
-       value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
-       padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
-
-       udelay(1);
-
-       value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-       value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
-       writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
-
        debug("< %s()\n", __func__);
        return 0;
 }
@@ -454,3 +440,35 @@ void tegra_xusb_padctl_init(void)
        ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
        debug("%s: done, ret=%d\n", __func__, ret);
 }
+
+void tegra_xusb_padctl_exit(void)
+{
+       u32 value;
+
+       debug("> %s\n", __func__);
+
+       value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX);
+       value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE;
+       value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
+       value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
+       value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
+       value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3;
+       value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4;
+       value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5;
+       value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6;
+       value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
+       padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
+
+       value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+       value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
+       value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
+       value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3);
+       value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
+       padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
+
+       reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
+       while (padctl.enable)
+               tegra_xusb_padctl_disable(&padctl);
+
+       debug("< %s()\n", __func__);
+}

diff --git a/arch/arm/mach-tegra/xusb-padctl-dummy.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c
index 3ec27a2e3aaf5848cc9a796922c6dc2a0491fdd6..f2d90302f6d2932beac4c839be5485e1272f0dbb 100644 (file)
--- a/arch/arm/mach-tegra/xusb-padctl-dummy.c
+++ b/arch/arm/mach-tegra/xusb-padctl-dummy.c
@@ -36,3 +36,7 @@ int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
 void __weak tegra_xusb_padctl_init(void)
 {
 }
+
+void __weak tegra_xusb_padctl_exit(void)
+{
+}