#include <asm/processor.h>
#include <linux/ctype.h>
#include <asm/io.h>
+#include <asm/fsl_fdt.h>
#include <asm/fsl_portals.h>
#include <hwconfig.h>
#ifdef CONFIG_FSL_ESDHC
return 1;
}
+
+void fdt_del_diu(void *blob)
+{
+ int nodeoff = 0;
+
+ while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+ "fsl,diu")) >= 0) {
+ fdt_del_node(blob, nodeoff);
+ }
+}
--- /dev/null
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _FSL_FDT_H_
+#define _FSL_FDT_H_
+
+void fdt_del_diu(void *blob);
+
+#endif
cpld_write(offsetof(struct cpld_data, reg), value)
#define MISC_CTL_SG_SEL 0x80
#define MISC_CTL_AURORA_SEL 0x02
+#define MISC_MUX_QE_TDM 0xc0
#include <common.h>
#include <command.h>
+#include <hwconfig.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
+#include <asm/fsl_fdt.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
#if defined(CONFIG_T1040D4RDB)
+ if (hwconfig("qe-tdm")) {
+ CPLD_WRITE(sfp_ctl_status, CPLD_READ(sfp_ctl_status) |
+ MISC_MUX_QE_TDM);
+ printf("QECSR : 0x%02x, mux to qe-tdm\n",
+ CPLD_READ(sfp_ctl_status));
+ }
/* Mask all CPLD interrupt sources, except QSGMII interrupts */
if (CPLD_READ(sw_ver) < 0x03) {
debug("CPLD SW version 0x%02x doesn't support int_mask\n",
fdt_fixup_fman_ethernet(blob);
#endif
+ if (hwconfig("qe-tdm"))
+ fdt_del_diu(blob);
return 0;
}