rockchip: spi: enable support for the rk_spi driver for the RK3368

For the RK3368, we can reuse the SPI driver (although we'll have to
eventually investigate whether it can be merged with the
designware_spi.c driver) also used for the RK3288 and RK3399.
This adds the necessary compatible string to support the RK3368.

Note that the assumption that GPLL will be clocked at 594MHz is not
true for the RK3368, but this will not lead to incorrect functioning
(just to a lower-than-expected SPI operating frequency): this has been
documented in the driver, so it doesn't cause any headaches when
someone next needs to touch the clock code of this driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
index 7921ea0d7542762bf9663d1b14ddff32fcf26994..c70d63627704cfded3d481128a555d88f7f4ed49 100644 (file)
--- a/drivers/spi/rk_spi.c
+++ b/drivers/spi/rk_spi.c
@@ -210,6 +210,14 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
 
 static int rockchip_spi_calc_modclk(ulong max_freq)
 {
+       /*
+        * While this is not strictly correct for the RK3368, as the
+        * GPLL will be 576MHz, things will still work, as the
+        * clk_set_rate(...) implementation in our clock-driver will
+        * chose the next closest rate not exceeding what we request
+        * based on the output of this function.
+        */
+
        unsigned div;
        const unsigned long gpll_hz = 594000000UL;
 
@@ -443,6 +451,7 @@ static const struct dm_spi_ops rockchip_spi_ops = {
 
 static const struct udevice_id rockchip_spi_ids[] = {
        { .compatible = "rockchip,rk3288-spi" },
+       { .compatible = "rockchip,rk3368-spi" },
        { .compatible = "rockchip,rk3399-spi" },
        { }
 };