microblaze: exception: fix unaligned data access register mask

The correct mask for getting the source/destination register from ESR in
the case of an unaligned access exception is 0x3E0. With this change, a
dummy unaligned store produces the expected info:
"""
>> swi r5, r0, 0x111

 ...
 Hardware exception at 0x111 address
 Unaligned data access exception
 Unaligned word access
 Unaligned store access
 Register R5
 Return address from exception 0x7f99dfc
 ### ERROR ### Please RESET the board ###
"""

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-6-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c
index d37f04364ad263bc0653b15e5c089e946de96f7b..d3640d3903b81e6d66e69d6af77180a1c44f7c73 100644 (file)
--- a/arch/microblaze/cpu/exception.c
+++ b/arch/microblaze/cpu/exception.c
@@ -38,7 +38,7 @@ void _hw_exception_handler (void)
 
                printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
                printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
-               printf("Register R%x\n", (state & 0x3E) >> 5);
+               printf("Register R%x\n", (state & 0x3E0) >> 5);
                break;
        case 0x2:
                puts("Illegal op-code exception\n");