ARM: imx: Update Data Modul i.MX8M Mini eDM SBC DRAM timing

Adjust the DRAM timing settings for this board per ones provided
by hardware department. The change is applied to the LPDDR4 MR11
register CA ODT configuration, from RZQ/6 to RZQ/3, which fixes
stability issues on subset of boards. The DDR PHY PIE block has
been updated accordingly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>

diff --git a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c
index c2abcb54895a1ae232dc6d6b05044aa06bad8d3a..f40fd48fc49ddeee3e31dceb3dca0d00daa2efb0 100644 (file)
--- a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c
+++ b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_2G_32.c
@@ -22,7 +22,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d4000d4, 0x940000 },
        { 0x3d4000dc, 0xd4002d },
        { 0x3d4000e0, 0x310000 },
-       { 0x3d4000e8, 0x66004d },
+       { 0x3d4000e8, 0x36004d },
        { 0x3d4000ec, 0x16004d },
        { 0x3d400100, 0x191e1920 },
        { 0x3d400104, 0x60630 },
@@ -55,6 +55,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d400204, 0x80808 },
        { 0x3d400214, 0x7070707 },
        { 0x3d400218, 0x7070707 },
+       { 0x3d40021c, 0xf0f },
        { 0x3d400250, 0x29001701 },
        { 0x3d400254, 0x2c },
        { 0x3d40025c, 0x4000030 },
@@ -72,7 +73,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d402064, 0xc001c },
        { 0x3d4020dc, 0x840000 },
        { 0x3d4020e0, 0x310000 },
-       { 0x3d4020e8, 0x66004d },
+       { 0x3d4020e8, 0x36004d },
        { 0x3d4020ec, 0x16004d },
        { 0x3d402100, 0xa040305 },
        { 0x3d402104, 0x30407 },
@@ -97,7 +98,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d403064, 0x30007 },
        { 0x3d4030dc, 0x840000 },
        { 0x3d4030e0, 0x310000 },
-       { 0x3d4030e8, 0x66004d },
+       { 0x3d4030e8, 0x36004d },
        { 0x3d4030ec, 0x16004d },
        { 0x3d403100, 0xa010102 },
        { 0x3d403104, 0x30404 },
@@ -1059,25 +1060,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
        { 0x54012, 0x110 },
        { 0x54019, 0x2dd4 },
        { 0x5401a, 0x31 },
-       { 0x5401b, 0x4d66 },
+       { 0x5401b, 0x4d36 },
        { 0x5401c, 0x4d00 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x2dd4 },
        { 0x54020, 0x31 },
-       { 0x54021, 0x4d66 },
+       { 0x54021, 0x4d36 },
        { 0x54022, 0x4d00 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x1 },
        { 0x54032, 0xd400 },
        { 0x54033, 0x312d },
-       { 0x54034, 0x6600 },
+       { 0x54034, 0x3600 },
        { 0x54035, 0x4d },
        { 0x54036, 0x4d },
        { 0x54037, 0x1600 },
        { 0x54038, 0xd400 },
        { 0x54039, 0x312d },
-       { 0x5403a, 0x6600 },
+       { 0x5403a, 0x3600 },
        { 0x5403b, 0x4d },
        { 0x5403c, 0x4d },
        { 0x5403d, 0x1600 },
@@ -1098,25 +1099,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
        { 0x54012, 0x110 },
        { 0x54019, 0x84 },
        { 0x5401a, 0x31 },
-       { 0x5401b, 0x4d66 },
+       { 0x5401b, 0x4d36 },
        { 0x5401c, 0x4d00 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x84 },
        { 0x54020, 0x31 },
-       { 0x54021, 0x4d66 },
+       { 0x54021, 0x4d36 },
        { 0x54022, 0x4d00 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x1 },
        { 0x54032, 0x8400 },
        { 0x54033, 0x3100 },
-       { 0x54034, 0x6600 },
+       { 0x54034, 0x3600 },
        { 0x54035, 0x4d },
        { 0x54036, 0x4d },
        { 0x54037, 0x1600 },
        { 0x54038, 0x8400 },
        { 0x54039, 0x3100 },
-       { 0x5403a, 0x6600 },
+       { 0x5403a, 0x3600 },
        { 0x5403b, 0x4d },
        { 0x5403c, 0x4d },
        { 0x5403d, 0x1600 },
@@ -1137,25 +1138,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
        { 0x54012, 0x110 },
        { 0x54019, 0x84 },
        { 0x5401a, 0x31 },
-       { 0x5401b, 0x4d66 },
+       { 0x5401b, 0x4d36 },
        { 0x5401c, 0x4d00 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x84 },
        { 0x54020, 0x31 },
-       { 0x54021, 0x4d66 },
+       { 0x54021, 0x4d36 },
        { 0x54022, 0x4d00 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x1 },
        { 0x54032, 0x8400 },
        { 0x54033, 0x3100 },
-       { 0x54034, 0x6600 },
+       { 0x54034, 0x3600 },
        { 0x54035, 0x4d },
        { 0x54036, 0x4d },
        { 0x54037, 0x1600 },
        { 0x54038, 0x8400 },
        { 0x54039, 0x3100 },
-       { 0x5403a, 0x6600 },
+       { 0x5403a, 0x3600 },
        { 0x5403b, 0x4d },
        { 0x5403c, 0x4d },
        { 0x5403d, 0x1600 },
@@ -1177,25 +1178,25 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
        { 0x54012, 0x110 },
        { 0x54019, 0x2dd4 },
        { 0x5401a, 0x31 },
-       { 0x5401b, 0x4d66 },
+       { 0x5401b, 0x4d36 },
        { 0x5401c, 0x4d00 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x2dd4 },
        { 0x54020, 0x31 },
-       { 0x54021, 0x4d66 },
+       { 0x54021, 0x4d36 },
        { 0x54022, 0x4d00 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x1 },
        { 0x54032, 0xd400 },
        { 0x54033, 0x312d },
-       { 0x54034, 0x6600 },
+       { 0x54034, 0x3600 },
        { 0x54035, 0x4d },
        { 0x54036, 0x4d },
        { 0x54037, 0x1600 },
        { 0x54038, 0xd400 },
        { 0x54039, 0x312d },
-       { 0x5403a, 0x6600 },
+       { 0x5403a, 0x3600 },
        { 0x5403b, 0x4d },
        { 0x5403c, 0x4d },
        { 0x5403d, 0x1600 },
@@ -1692,15 +1693,15 @@ static struct dram_cfg_param ddr_phy_pie[] = {
        { 0x400d6, 0x20a },
        { 0x400d7, 0x20b },
        { 0x2003a, 0x2 },
-       { 0x2000b, 0x5d },
+       { 0x2000b, 0x34b },
        { 0x2000c, 0xbb },
        { 0x2000d, 0x753 },
        { 0x2000e, 0x2c },
-       { 0x12000b, 0xc },
+       { 0x12000b, 0x70 },
        { 0x12000c, 0x19 },
        { 0x12000d, 0xfa },
        { 0x12000e, 0x10 },
-       { 0x22000b, 0x3 },
+       { 0x22000b, 0x1c },
        { 0x22000c, 0x6 },
        { 0x22000d, 0x3e },
        { 0x22000e, 0x10 },

diff --git a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c
index e44c1ea27722800fa328d7e2c769d35a80a02099..0e5be8efd004d3952fbdc431e9c5bb300fdb05b2 100644 (file)
--- a/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c
+++ b/board/data_modul/imx8mm_edm_sbc/lpddr4_timing_4G_32.c
@@ -22,7 +22,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d4000d4, 0x940000 },
        { 0x3d4000dc, 0xd4002d },
        { 0x3d4000e0, 0x310000 },
-       { 0x3d4000e8, 0x66004d },
+       { 0x3d4000e8, 0x36004d },
        { 0x3d4000ec, 0x16004d },
        { 0x3d400100, 0x191e1920 },
        { 0x3d400104, 0x60630 },
@@ -55,6 +55,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d400204, 0x80808 },
        { 0x3d400214, 0x7070707 },
        { 0x3d400218, 0x7070707 },
+       { 0x3d40021c, 0xf0f },
        { 0x3d400250, 0x29001701 },
        { 0x3d400254, 0x2c },
        { 0x3d40025c, 0x4000030 },
@@ -72,7 +73,7 @@ static struct dram_cfg_param ddr_ddrc_cfg[] = {
        { 0x3d402064, 0xc001c },
        { 0x3d4020dc, 0x840000 },
        { 0x3d4020e0, 0x310000 },
-       { 0x3d4020e8, 0x66004d },
+       { 0x3d4020e8, 0x36004d },
        { 0x3d4020ec, 0x16004d },
        { 0x3d402100, 0xa040305 },
        { 0x3d402104, 0x30407 },
@@ -1059,25 +1060,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
        { 0x54012, 0x310 },
        { 0x54019, 0x2dd4 },
        { 0x5401a, 0x31 },
-       { 0x5401b, 0x4d66 },
+       { 0x5401b, 0x4d36 },
        { 0x5401c, 0x4d00 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x2dd4 },
        { 0x54020, 0x31 },
-       { 0x54021, 0x4d66 },
+       { 0x54021, 0x4d36 },
        { 0x54022, 0x4d00 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x3 },
        { 0x54032, 0xd400 },
        { 0x54033, 0x312d },
-       { 0x54034, 0x6600 },
+       { 0x54034, 0x3600 },
        { 0x54035, 0x4d },
        { 0x54036, 0x4d },
        { 0x54037, 0x1600 },
        { 0x54038, 0xd400 },
        { 0x54039, 0x312d },
-       { 0x5403a, 0x6600 },
+       { 0x5403a, 0x3600 },
        { 0x5403b, 0x4d },
        { 0x5403c, 0x4d },
        { 0x5403d, 0x1600 },
@@ -1098,25 +1099,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
        { 0x54012, 0x310 },
        { 0x54019, 0x84 },
        { 0x5401a, 0x31 },
-       { 0x5401b, 0x4d66 },
+       { 0x5401b, 0x4d36 },
        { 0x5401c, 0x4d00 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x84 },
        { 0x54020, 0x31 },
-       { 0x54021, 0x4d66 },
+       { 0x54021, 0x4d36 },
        { 0x54022, 0x4d00 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x3 },
        { 0x54032, 0x8400 },
        { 0x54033, 0x3100 },
-       { 0x54034, 0x6600 },
+       { 0x54034, 0x3600 },
        { 0x54035, 0x4d },
        { 0x54036, 0x4d },
        { 0x54037, 0x1600 },
        { 0x54038, 0x8400 },
        { 0x54039, 0x3100 },
-       { 0x5403a, 0x6600 },
+       { 0x5403a, 0x3600 },
        { 0x5403b, 0x4d },
        { 0x5403c, 0x4d },
        { 0x5403d, 0x1600 },
@@ -1172,31 +1173,30 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
        { 0x54008, 0x61 },
        { 0x54009, 0xc8 },
        { 0x5400b, 0x2 },
-       { 0x5400d, 0x100 },
        { 0x5400f, 0x100 },
        { 0x54010, 0x1f7f },
        { 0x54012, 0x310 },
        { 0x54019, 0x2dd4 },
        { 0x5401a, 0x31 },
-       { 0x5401b, 0x4d66 },
+       { 0x5401b, 0x4d36 },
        { 0x5401c, 0x4d00 },
        { 0x5401e, 0x16 },
        { 0x5401f, 0x2dd4 },
        { 0x54020, 0x31 },
-       { 0x54021, 0x4d66 },
+       { 0x54021, 0x4d36 },
        { 0x54022, 0x4d00 },
        { 0x54024, 0x16 },
        { 0x5402b, 0x1000 },
        { 0x5402c, 0x3 },
        { 0x54032, 0xd400 },
        { 0x54033, 0x312d },
-       { 0x54034, 0x6600 },
+       { 0x54034, 0x3600 },
        { 0x54035, 0x4d },
        { 0x54036, 0x4d },
        { 0x54037, 0x1600 },
        { 0x54038, 0xd400 },
        { 0x54039, 0x312d },
-       { 0x5403a, 0x6600 },
+       { 0x5403a, 0x3600 },
        { 0x5403b, 0x4d },
        { 0x5403c, 0x4d },
        { 0x5403d, 0x1600 },
@@ -1693,15 +1693,15 @@ static struct dram_cfg_param ddr_phy_pie[] = {
        { 0x400d6, 0x20a },
        { 0x400d7, 0x20b },
        { 0x2003a, 0x2 },
-       { 0x2000b, 0x5d },
+       { 0x2000b, 0x34b },
        { 0x2000c, 0xbb },
        { 0x2000d, 0x753 },
        { 0x2000e, 0x2c },
-       { 0x12000b, 0xc },
+       { 0x12000b, 0x70 },
        { 0x12000c, 0x19 },
        { 0x12000d, 0xfa },
        { 0x12000e, 0x10 },
-       { 0x22000b, 0x3 },
+       { 0x22000b, 0x1c },
        { 0x22000c, 0x6 },
        { 0x22000d, 0x3e },
        { 0x22000e, 0x10 },
@@ -1715,6 +1715,10 @@ static struct dram_cfg_param ddr_phy_pie[] = {
        { 0x90013, 0x6152 },
        { 0x20010, 0x5a },
        { 0x20011, 0x3 },
+       { 0x120010, 0x5a },
+       { 0x120011, 0x3 },
+       { 0x220010, 0x5a },
+       { 0x220011, 0x3 },
        { 0x40080, 0xe0 },
        { 0x40081, 0x12 },
        { 0x40082, 0xe0 },