]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
imx: ventana: enable dm support for PCI and FEC ethernet
authorTim Harvey <tharvey@gateworks.com>
Mon, 3 May 2021 18:21:27 +0000 (11:21 -0700)
committerStefano Babic <sbabic@denx.de>
Wed, 9 Jun 2021 11:33:35 +0000 (13:33 +0200)
Enable driver model support for FEC ethernet which allows us to remove
the iomux and board_eth_init function. Replace the toggling of the ethernet
phy reset with dt configuration.

Enable driver model support for PCI which allows us to remove the
eth1000_initialize() call. Additionally enable PCI_INIT_R to scan for
PCI devices on init such as the e1000 that is present on the GW552x.

Convert board_pci_fixup to use dm callback and remove pcidisable env
variable which is not supported for DM_PCI and thus leave PCI always
enabled during init.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
17 files changed:
arch/arm/dts/imx6qdl-gw51xx.dtsi
arch/arm/dts/imx6qdl-gw52xx.dtsi
arch/arm/dts/imx6qdl-gw53xx.dtsi
arch/arm/dts/imx6qdl-gw54xx.dtsi
arch/arm/dts/imx6qdl-gw560x.dtsi
arch/arm/dts/imx6qdl-gw5903.dtsi
arch/arm/dts/imx6qdl-gw5904.dtsi
arch/arm/dts/imx6qdl-gw5907.dtsi
arch/arm/dts/imx6qdl-gw5910.dtsi
arch/arm/dts/imx6qdl-gw5912.dtsi
arch/arm/dts/imx6qdl-gw5913.dtsi
board/gateworks/gw_ventana/common.h
board/gateworks/gw_ventana/gw_ventana.c
configs/gwventana_emmc_defconfig
configs/gwventana_gw5904_defconfig
configs/gwventana_nand_defconfig
include/configs/gw_ventana.h

index 2a21c6731ef41611d6497ffb0fac71f368fec2a0..7e28463084a69d16531c8bf05701f95655f90a95 100644 (file)
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
        phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <10>;
+       phy-reset-post-delay = <100>;
        status = "okay";
 };
 
index 6eedf8d40d87185f89338798d1062947edc25aa2..f1d9ba1fac6a7026d764268cf977ecfe26c87852 100644 (file)
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
        phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <10>;
+       phy-reset-post-delay = <100>;
        status = "okay";
 };
 
index 9deec7e352d5a7d3941ee039e599bee4dcc30f20..172a45ba17803e343d86afbe5862f93016002b4c 100644 (file)
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
        phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <10>;
+       phy-reset-post-delay = <100>;
        status = "okay";
 };
 
                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
                        MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                       MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
                >;
        };
 
index a30ba4848e04548b726d93716df80fa1467f5ee7..e09fad6068ca5d5f3ff240f48c0104cbe11cae02 100644 (file)
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
        phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <10>;
+       phy-reset-post-delay = <100>;
        status = "okay";
 };
 
                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
                        MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                       MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
                >;
        };
 
index 0786b0d5463a78ad19cfc80f540bc46490458294..bfe65fd3c09bc0129f0b62698fee3fb78c3fd5c9 100644 (file)
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
        phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <10>;
+       phy-reset-post-delay = <100>;
        status = "okay";
 };
 
index 78f9ec90b7cba03ca4c8fd37d0466fd5ec0fdf7e..6ebf6aef2f7dcc45f91ba9b49a8be36ce6dcdaef 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
+       phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <10>;
+       phy-reset-post-delay = <100>;
        status = "okay";
 };
 
index 5b7bd5693286a1defbdc82db1a352d6858272bc4..9adbd728dce822ee7bcdf7486d07c064ed957de0 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
+       phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <10>;
+       phy-reset-post-delay = <100>;
        status = "okay";
 
        fixed-link {
index c8b29246b787c369d7dcb85bab7aa3e2cf799397..58f73a141e4c4f4d9e46bc5527e74af413148337 100644 (file)
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
        phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <10>;
+       phy-reset-post-delay = <100>;
        status = "okay";
 };
 
index 248e077a56edf362d5da5ee15c0cde5360ab5d51..446c1043a7687ecea851d3554fe20c53b2b6140b 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
+       phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <10>;
+       phy-reset-post-delay = <100>;
        status = "okay";
 };
 
index 7593872c07e8612f43249be0ee50d7274378b21f..88234a6f1342f4971d841d785c158b7ccda7879c 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
+       phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <10>;
+       phy-reset-post-delay = <100>;
        status = "okay";
 };
 
                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                       MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
                >;
        };
 
index 9fae4cccd705c216074f46751311322a0898af2b..f4c2b2189f00bdc6b666bc089bc03e811a4cc73b 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
        phy-mode = "rgmii-id";
+       phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+       phy-reset-duration = <10>;
+       phy-reset-post-delay = <100>;
        status = "okay";
 };
 
index d73850c5b903b740a10414addf803bda2f1f4009..813f7d9f5622e589a512d1ccbdd4248d9104d2ee 100644 (file)
@@ -11,7 +11,6 @@
 #include "ventana_eeprom.h"
 
 /* GPIO's common to all baseboards */
-#define GP_PHY_RST     IMX_GPIO_NR(1, 30)
 #define GP_RS232_EN    IMX_GPIO_NR(2, 11)
 #define GP_MSATA_SEL   IMX_GPIO_NR(2, 8)
 
index 5237f2dac431806dec79de08c98df8f31551502b..1ed9c1a39f460a6147678a0c02af8d811ab4fb00 100644 (file)
@@ -31,7 +31,6 @@
 #include <linux/ctype.h>
 #include <miiphy.h>
 #include <mtd_node.h>
-#include <netdev.h>
 #include <pci.h>
 #include <linux/delay.h>
 #include <linux/libfdt.h>
@@ -54,42 +53,6 @@ DECLARE_GLOBAL_DATA_PTR;
 struct ventana_board_info ventana_info;
 static int board_type;
 
-/* ENET */
-static iomux_v3_cfg_t const enet_pads[] = {
-       IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
-                  MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
-                  MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
-                  MUX_PAD_CTRL(ENET_PAD_CTRL)),
-       /* PHY nRST */
-       IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
-};
-
-static void setup_iomux_enet(int gpio)
-{
-       SETUP_IOMUX_PADS(enet_pads);
-
-       /* toggle PHY_RST# */
-       gpio_request(gpio, "phy_rst#");
-       gpio_direction_output(gpio, 0);
-       mdelay(10);
-       gpio_set_value(gpio, 1);
-       mdelay(100);
-}
-
 #ifdef CONFIG_USB_EHCI_MX6
 /* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
 int board_ehci_hcd_init(int port)
@@ -195,40 +158,7 @@ int mv88e61xx_hw_reset(struct phy_device *phydev)
 }
 #endif // CONFIG_MV88E61XX_SWITCH
 
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_FEC_MXC
-       struct ventana_board_info *info = &ventana_info;
-
-       if (test_bit(EECONFIG_ETH0, info->config)) {
-               setup_iomux_enet(GP_PHY_RST);
-               cpu_eth_init(bis);
-       }
-#endif
-
-#ifdef CONFIG_E1000
-       e1000_initialize(bis);
-#endif
-
-#ifdef CONFIG_CI_UDC
-       /* For otg ethernet*/
-       usb_eth_initialize(bis);
-#endif
-
-       /* default to the first detected enet dev */
-       if (!env_get("ethprime")) {
-               struct eth_device *dev = eth_get_dev_by_index(0);
-               if (dev) {
-                       env_set("ethprime", dev->name);
-                       printf("set ethprime to %s\n", env_get("ethprime"));
-               }
-       }
-
-       return 0;
-}
-
 #if defined(CONFIG_VIDEO_IPUV3)
-
 static void enable_hdmi(struct display_info_t const *dev)
 {
        imx_enable_hdmi_phy();
@@ -427,7 +357,6 @@ int power_init_board(void)
        return 0;
 }
 
-#if defined(CONFIG_CMD_PCI)
 int imx6_pcie_toggle_reset(void)
 {
        if (board_type < GW_UNKNOWN) {
@@ -448,6 +377,7 @@ int imx6_pcie_toggle_reset(void)
 #define MAX_PCI_DEVS   32
 struct pci_dev {
        pci_dev_t devfn;
+       struct udevice *dev;
        unsigned short vendor;
        unsigned short device;
        unsigned short class;
@@ -458,18 +388,21 @@ struct pci_dev pci_devs[MAX_PCI_DEVS];
 int pci_devno;
 int pci_bridgeno;
 
-void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
-                        unsigned short vendor, unsigned short device,
-                        unsigned short class)
+void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev)
 {
-       int i;
-       u32 dw;
+       struct pci_child_plat *pdata = dev_get_parent_plat(udev);
        struct pci_dev *pdev = &pci_devs[pci_devno++];
+       unsigned short vendor = pdata->vendor;
+       unsigned short device = pdata->device;
+       unsigned int class = pdata->class;
+       pci_dev_t dev = dm_pci_get_bdf(udev);
+       int i;
 
        debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
              PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
 
        /* store array of devs for later use in device-tree fixup */
+       pdev->dev = udev;
        pdev->devfn = dev;
        pdev->vendor = vendor;
        pdev->device = device;
@@ -496,19 +429,19 @@ void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
        if (vendor == PCI_VENDOR_ID_PLX &&
            (device & 0xfff0) == 0x8600 &&
            PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
+               ulong val;
                debug("configuring PLX 860X downstream PERST#\n");
-               pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
-               dw |= 0xaaa8; /* GPIO1-7 outputs */
-               pci_hose_write_config_dword(hose, dev, 0x62c, dw);
+               pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32);
+               val |= 0xaaa8; /* GPIO1-7 outputs */
+               pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32);
 
-               pci_hose_read_config_dword(hose, dev, 0x644, &dw);
-               dw |= 0xfe;   /* GPIO1-7 output high */
-               pci_hose_write_config_dword(hose, dev, 0x644, dw);
+               pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32);
+               val |= 0xfe;   /* GPIO1-7 output high */
+               pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32);
 
                mdelay(100);
        }
 }
-#endif /* CONFIG_CMD_PCI */
 
 #ifdef CONFIG_SERIAL_TAG
 /*
index 97b39b6e724df081a6b021155649961f14eef756..6e3aebbf1bdd3dff599d9c9452626cf9a46eb52d 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_MISC_INIT_R=y
+CONFIG_PCI_INIT_R=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
@@ -85,9 +86,13 @@ CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_FSL_USDHC=y
 CONFIG_MTD=y
 CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_DM_PCI=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_REGULATOR=y
index ce40a4d85b83776063e7384cc7f5b8c9077f7ded..77e65f223688429836a34533a56696de00b85b35 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_MISC_INIT_R=y
+CONFIG_PCI_INIT_R=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
@@ -89,9 +90,13 @@ CONFIG_MV88E61XX_SWITCH=y
 CONFIG_MV88E61XX_CPU_PORT=5
 CONFIG_MV88E61XX_PHY_PORTS=0xf
 CONFIG_MV88E61XX_FIXED_PORTS=0x0
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_DM_PCI=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_REGULATOR=y
index a4d85956a041cdecb036cd8dff2555adf28db4cb..db31d97f3d0fd58c9eb8aae7ac3d3970ca6ee98f 100644 (file)
@@ -34,6 +34,7 @@ CONFIG_USE_PREBOOT=y
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_MISC_INIT_R=y
+CONFIG_PCI_INIT_R=y
 CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_FIT_IMAGE_TINY=y
@@ -91,9 +92,13 @@ CONFIG_MTD_RAW_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_NAND_MXS_DT=y
 CONFIG_PHYLIB=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
 CONFIG_E1000=y
+CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_DM_PCI=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_REGULATOR=y
index 5754b6aef05d0e81f7c2ccf9d9c5ab4f8b24fb72..4f2f323b777477e0356ee75aec6a150bb6caa44f 100644 (file)
@@ -65,8 +65,6 @@
  * PCI express
  */
 #ifdef CONFIG_CMD_PCI
-#define CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCI_FIXUP_DEV
 #define CONFIG_PCIE_IMX
 #endif
 
 
 /* Various command support */
 
-/* Ethernet support */
-#define CONFIG_FEC_MXC
-#define IMX_FEC_BASE             ENET_BASE_ADDR
-#define CONFIG_FEC_XCV_TYPE      RGMII
-#define CONFIG_FEC_MXC_PHYADDR   0
-#define CONFIG_ARP_TIMEOUT       200UL
-
 /* USB Configs */
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET  /* For OTG port */
 #define CONFIG_MXC_USB_PORTSC     (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_SERVERIP           192.168.1.146
 
 #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
-       "pcidisable=1\0" \
        "splashpos=m,m\0" \
        "usb_pgood_delay=2000\0" \
        "console=ttymxc1\0" \