net: gem: Enable MDIO bus earlier

Enable access to MDIO before zynq_gem_init is called.
It enables read information about phy earlier.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index d5540ec2155c719d3c4a4a1e1f707734b8f034ee..9ce1221e8d0f2e92022a58ecae11fd8bac7e0e4e 100644 (file)
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -314,6 +314,7 @@ static int zynq_phy_init(struct eth_device *dev)
 {
        int ret;
        struct zynq_gem_priv *priv = dev->priv;
+       struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
        const u32 supported = SUPPORTED_10baseT_Half |
                        SUPPORTED_10baseT_Full |
                        SUPPORTED_100baseT_Half |
@@ -321,6 +322,9 @@ static int zynq_phy_init(struct eth_device *dev)
                        SUPPORTED_1000baseT_Half |
                        SUPPORTED_1000baseT_Full;
 
+       /* Enable only MDIO bus */
+       writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
+
        ret = phy_detection(dev);
        if (ret) {
                printf("GEM PHY init failed\n");
@@ -343,7 +347,6 @@ static int zynq_phy_init(struct eth_device *dev)
 static int zynq_gem_init(struct eth_device *dev, bd_t *bis)
 {
        u32 i;
-       int ret;
        unsigned long clk_rate = 0;
        struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
        struct zynq_gem_priv *priv = dev->priv;
@@ -411,10 +414,6 @@ static int zynq_gem_init(struct eth_device *dev, bd_t *bis)
                priv->init++;
        }
 
-       ret = zynq_phy_init(dev);
-       if (ret)
-               return ret;
-
        phy_startup(priv->phydev);
 
        if (!priv->phydev->link) {
@@ -597,6 +596,7 @@ static int zynq_gem_miiphy_write(const char *devname, uchar addr,
 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
                        int phy_addr, u32 emio)
 {
+       int ret;
        struct eth_device *dev;
        struct zynq_gem_priv *priv;
        void *bd_space;
@@ -650,6 +650,10 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
        miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
        priv->bus = miiphy_get_dev_by_name(dev->name);
 
+       ret = zynq_phy_init(dev);
+       if (ret)
+               return ret;
+
        return 1;
 }