arm: lpc32xx: Fix timer initialization

The match controller register is not cleared during
initialization. However, some bits of this register may reset the TC if
tnMRx match it.

As we can't make any assumption about how U-Boot is launched by the first
stage bootloader (such as S1L) clearing this register ensure that the
timers work as expected.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
index 404ccbb7163bdc612805210a5d80bc6d010f5c63..b3ca68604098137a1dbddbaf9cd8cf371ca4033b 100644 (file)
--- a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c
@@ -33,6 +33,9 @@ static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq)
 
        /* Set prescale counter value */
        writel((get_periph_clk_rate() / freq) - 1, &timer->pr);
+
+       /* Ensure that the counter is not reset when matching TC */
+       writel(0,  &timer->mcr);
 }
 
 static void lpc32xx_timer_count(struct timer_regs *timer, int enable)