arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

The DMA, QSPI, and SD/MMC reset bits are located in the permodrst register,
not the mpumodrst. So the bank for these reset bits should be 1, not 0.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 8e59578f374b7f799a36a3998b4f874beddd5d5d..666a2ef8dfc7d5599aaa21a8d3bc6c39aa96e8d2 100644 (file)
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -69,9 +69,9 @@ struct socfpga_reset_manager {
 #define RSTMGR_UART0           RSTMGR_DEFINE(1, 16)
 #define RSTMGR_SPIM0           RSTMGR_DEFINE(1, 18)
 #define RSTMGR_SPIM1           RSTMGR_DEFINE(1, 19)
-#define RSTMGR_QSPI            RSTMGR_DEFINE(0, 5)
-#define RSTMGR_SDMMC           RSTMGR_DEFINE(0, 22)
-#define RSTMGR_DMA             RSTMGR_DEFINE(0, 28)
+#define RSTMGR_QSPI            RSTMGR_DEFINE(1, 5)
+#define RSTMGR_SDMMC           RSTMGR_DEFINE(1, 22)
+#define RSTMGR_DMA             RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR             RSTMGR_DEFINE(1, 29)
 
 /* Create a human-readable reference to SoCFPGA reset. */