clk: at91: sam9x60: Add initial setup of UPLL and USBCK rates

In order for some of the functionalities, such as the USB clocks,
to work properly we need some clocks to be properly initialised
at the very beginning of booting.

Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>

diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index 14c2ffcac18bc306b3e985a0a8c88404733bb34b..e2f72446d500cdaec2b3f25ae91ca8d639955863 100644 (file)
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -378,6 +378,31 @@ static const struct {
        { .n = "dbgu_gclk",   .id = 47, },
 };
 
+/**
+ * Clock setup description
+ * @cid:       clock id corresponding to clock subsystem
+ * @pid:       parent clock id corresponding to clock subsystem
+ * @rate:      clock rate
+ * @prate:     parent rate
+ */
+static const struct pmc_clk_setup sam9x60_clk_setup[] = {
+       {
+               .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_FRAC),
+               .rate = 960000000,
+       },
+
+       {
+               .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV),
+               .rate = 480000000,
+       },
+
+       {
+               .cid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_USBCK),
+               .pid = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV),
+               .rate = 48000000,
+       },
+};
+
 #define prepare_mux_table(_allocs, _index, _dst, _src, _num, _label)   \
        do {                                                            \
                int _i;                                                 \
@@ -668,6 +693,11 @@ static int sam9x60_clk_probe(struct udevice *dev)
                clk_dm(AT91_TO_CLK_ID(PMC_TYPE_GCK, sam9x60_gck[i].id), c);
        }
 
+       /* Setup clocks. */
+       ret = at91_clk_setup(sam9x60_clk_setup, ARRAY_SIZE(sam9x60_clk_setup));
+       if (ret)
+               goto fail;
+
        return 0;
 
 fail: