spl: introduce SPL_XIP to config

U-Boot and SPL don't necessary share the same location, so we might end
with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory.

In case of non XIP boot mode, we rely on such variables as "hart_lottery"
and "available_harts_lock" which we use as atomics.

The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL,
so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes.

This adds an option special for SPL to behave it in XIP manner and we don't
use hart_lottery and available_harts_lock, during start proccess.

Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 78e964db129a251aa9acb0ced000b74bb1ce93a8..c042506a644a9c95dc14a88df96320b33416f8e9 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -269,6 +269,13 @@ config XIP
          from a NOR flash memory without copying the code to ram.
          Say yes here if U-Boot boots from flash directly.
 
+config SPL_XIP
+       bool "Enable XIP mode for SPL"
+       help
+         If SPL starts in read-only memory (XIP for example) then we shouldn't
+         rely on lock variables (for example hart_lottery and available_harts_lock),
+         this affects only SPL, other stages should proceed as non-XIP.
+
 config SHOW_REGS
        bool "Show registers on unhandled exception"
 

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 3ffcbbd23fa62f4b198ccfd2531fbed0139fe5fa..0f323b26b3f896fad99fb1cf8ac3e937c2eeb9e4 100644 (file)
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -19,7 +19,7 @@
  * The variables here must be stored in the data section since they are used
  * before the bss section is available.
  */
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
 u32 hart_lottery __section(".data") = 0;
 
 /*

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index b7f21ab63e00cbd117def75ca5a122a2e67fccd2..de9d078da144c30bd1f1cd644f96db0d02d17662 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -122,7 +122,7 @@ call_board_init_f_0:
 call_harts_early_init:
        jal     harts_early_init
 
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
        /*
         * Pick hart to initialize global data and run U-Boot. The other harts
         * wait for initialization to complete.
@@ -152,7 +152,7 @@ call_harts_early_init:
        /* save the boot hart id to global_data */
        SREG    tp, GD_BOOT_HART(gp)
 
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
        la      t0, available_harts_lock
        amoswap.w.rl zero, zero, 0(t0)
 

diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 095484a63586d41f5a3c04883aeb6eca6c524fb9..b3c79e176017bba80c5eca7930bf48eef498969d 100644 (file)
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -27,7 +27,7 @@ struct arch_global_data {
 #if CONFIG_IS_ENABLED(SMP)
        struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
        ulong available_harts;
 #endif
 };

diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f1fe089b3d8fd99434748c767f4b63530e0ee6c8..c4f48c83735474e234e0c85170c39557970dbdd5 100644 (file)
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -16,7 +16,7 @@ int main(void)
 {
        DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
        DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr));
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
        DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
 #endif
 

diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index ba992100adf1c569152d852f1c843c794a6c9d07..f8b756291f3565213f9c5daebdcfa4b18f3fefc2 100644 (file)
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -45,7 +45,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait)
                        continue;
                }
 
-#ifndef CONFIG_XIP
+#if !CONFIG_IS_ENABLED(XIP)
                /* skip if hart is not available */
                if (!(gd->arch.available_harts & (1 << reg)))
                        continue;

diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index c7b6ea4730dfa1561854546efa2762fdfbb17c4e..67c1e35c557c0f67318d687bc25dc501cb97faa3 100644 (file)
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -11,7 +11,7 @@ CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x100000
 CONFIG_TARGET_AX25_AE350=y
 CONFIG_RISCV_SMODE=y
-CONFIG_XIP=y
+CONFIG_SPL_XIP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00

diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index a197c97736b6281c6557cc95361132ba3e781caf..baee9bfe4a59b34e3d0bbb996745e14001aad672 100644 (file)
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -12,7 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000
 CONFIG_TARGET_AX25_AE350=y
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
-CONFIG_XIP=y
+CONFIG_SPL_XIP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70