# SPDX-License-Identifier: GPL-2.0+
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
+ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
CONFIG_CPU_V7A=
CONFIG_CPU_ARM720T=y
endif
# On Tegra systems we must build SPL for the armv4 core on the device
# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
+ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_ARCH_TEGRA),yy)
arch-y += -D__LINUX_ARM_ARCH__=4
else
arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
head-y := arch/arm/cpu/$(CPU)/start.o
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
ifeq ($(CONFIG_SYS_SOC)$(CONFIG_SPL_FRAMEWORK),"mxs")
head-y := arch/arm/cpu/arm926ejs/mxs/start.o
endif
ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
# This file is parsed many times, so the string may get added multiple
# times. Also, the prefix needs to be different based on whether
-# CONFIG_SPL_BUILD is defined or not. 'filter-out' the existing entry
+# CONFIG_XPL_BUILD is defined or not. 'filter-out' the existing entry
# before adding the correct one.
PLATFORM_LIBS := arch/arm/lib/eabi_compat.o \
$(filter-out arch/arm/lib/eabi_compat.o, $(PLATFORM_LIBS))
endif
endif
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
# Check that only R_ARM_RELATIVE relocations are generated.
INPUTS-y += checkarmreloc
# The movt / movw can hardcode 16 bit parts of the addresses in the
ifdef CONFIG_MACH_IMX
ifneq ($(CONFIG_IMX_CONFIG),"")
ifdef CONFIG_SPL
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
INPUTS-y += SPL
endif
else
obj-y = cpu.o
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_EFI_LOADER) += sctlr.o
endif
* When booting from NAND - it has definitely been a reset, so, no need
* to flush caches and disable the MMU
*/
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/*
* flush v4 I/D caches
*/
extra-y = start.o
obj-y = cpu.o cache.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifdef CONFIG_SPL_NO_CPU_SUPPORT
extra-y :=
endif
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-extra-$(CONFIG_SPL_BUILD) := start.o
+extra-$(CONFIG_XPL_BUILD) := start.o
obj-y = clock.o mxs.o iomux.o timer.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
endif
# Build a combined spl + u-boot image
ifdef CONFIG_SPL
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
ALL-y += u-boot-sunxi-with-spl.bin
endif
endif
obj-$(CONFIG_SYS_ARM_MPU) += mpu_v7r.o
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_EFI_LOADER) += sctlr.o
obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
endif
*
* we turn off caches etc ...
*/
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
disable_interrupts();
#endif
/*
* Setup a temporary stack. Global data is not available yet.
*/
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr sp, =CONFIG_SPL_STACK
#else
ldr sp, =SYS_INIT_SP_ADDR
* Set up global data for boards that still need it. This will be
* removed soon.
*/
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
ldr r9, =gdata
#else
sub sp, sp, #GD_SIZE
obj-$(CONFIG_S5P4418_ONEWIRE) += pwm.o
else
obj-y += cpu_info.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += timer.o
obj-y += sromc.o
endif
orr r2, r4, r2 @ r2 has combined CPU variant + revision
/* Early stack for ERRATA that needs into call C code */
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#else
ldr r0, =(SYS_INIT_SP_ADDR)
obj-$(CONFIG_MACH_SUN6I) += sram.o
obj-$(CONFIG_MACH_SUN8I) += sram.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += fel_utils.o
endif
obj-y += cache_v8.o
obj-y += cache.o
endif
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o
else
obj-y += exceptions.o
obj-y += cpu-dt.o
obj-$(CONFIG_ARM_SMCCC) += smccc-call.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o
else
obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o
endif
obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_RECOVER_DATA_SECTION) += spl_data.o
endif
* running however really wants to have dcache and the MMU active. Check that
* everything is sane and give the developer a hint if it isn't.
*/
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
#endif
obj-y += cpu.o
obj-y += lowlevel.o
obj-y += soc.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_MP) += mp.o spintable.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
endif
{ CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
CFG_SYS_FSL_DRAM_SIZE1,
#if defined(CONFIG_TFABOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
+ (defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD))
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
{ CFG_SYS_FSL_DRAM_BASE1, CFG_SYS_FSL_DRAM_BASE1,
CFG_SYS_FSL_DRAM_SIZE1,
#if defined(CONFIG_TFABOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
+ (defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD))
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
{
int error = 0;
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
error = fsl_mc_ldpaa_init(bis);
#endif
return error;
{
phys_size_t ram_top = ram_size;
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
ram_top = mc_get_dram_block_size();
if (ram_top > ram_size)
return ram_size + ram_top;
if (i > 0)
ret = 0;
-#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bd->bi_dram[2].size >=
}
#endif /* CFG_SYS_MEM_RESERVE_SECURE */
-#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESV_RAM) && !defined(CONFIG_XPL_BUILD)
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bd->bi_dram[2].size >=
#ifdef CONFIG_SYS_FSL_DDR
fsl_initdram();
#if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
- defined(CONFIG_SPL_BUILD)
+ defined(CONFIG_XPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
#define HWA_CGA_M1_CLK_SEL 0xe0000000
#define HWA_CGA_M1_CLK_SHIFT 29
-#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD)
rcw_tmp = in_be32(&gur->rcwsr[7]);
switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
case 2:
static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
#endif
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
int xfi_dpmac[XFI14 + 1];
int sgmii_dpmac[SGMII18 + 1];
debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
else {
serdes_prtcl_map[lane_prtcl] = 1;
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
void fsl_serdes_init(void)
{
-#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_XPL_BUILD)
int i , j;
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
}
-#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD)
static void set_fman_icids(struct fman_icid_id_table *tbl, int size)
{
int i;
/* setup general icid offsets */
set_icid(icid_tbl, icid_tbl_sz);
-#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD)
set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
#endif
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids)
{
int i, ret;
#endif
/* Initialize GIC Secure Bank Status */
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
branch_if_slave x0, 1f
bl get_gic_offset
#endif
#if !defined(CONFIG_TFABOOT) && \
- (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD))
+ (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_XPL_BUILD))
bl fsl_ocram_init
#endif
ret
ENDPROC(lowlevel_init)
-#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_XPL_BUILD)
ENTRY(fsl_ocram_init)
mov x28, lr /* Save LR */
bl fsl_clear_ocram
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
-#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD)
struct fman_icid_id_table fman_icid_tbl[] = {
/* port id, icid */
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
-#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_XPL_BUILD)
struct fman_icid_id_table fman_icid_tbl[] = {
/* port id, icid */
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_board_init(void)
{
return 1;
}
#endif /* CONFIG_SPL_OS_BOOT */
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
.globl save_boot_params_ret
save_boot_params_ret:
-#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_SPL_BUILD)
+#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_XPL_BUILD)
/* Verify that we're 4K aligned. */
adr x0, _start
ands x0, x0, #0xfff
pie_fixup_done:
#endif
-#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_XPL_BUILD)
.macro set_vbar, regname, reg
msr \regname, \reg
.endm
/* Processor specific initialization */
bl lowlevel_init
-#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_XPL_BUILD)
branch_if_master x0, master_cpu
b spin_table_secondary_jump
/* never return */
/*-----------------------------------------------------------------------*/
ENTRY(c_runtime_cpu_setup)
-#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_XPL_BUILD)
/* Relocate vBAR */
adr x0, vectors
switch_el x1, 3f, 2f, 1f
};
&binman {
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
};
&binman {
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
#include <asm/armv8/sec_firmware.h>
struct icid_id_table {
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
const char *compat;
phys_addr_t compat_addr;
#endif
phys_addr_t reg_addr;
u32 reg;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
u32 id;
#endif
bool le;
void set_icids(void);
void fdt_fixup_icid(void *blob);
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr, _le) \
{ .reg = regA, \
.reg_addr = addr, \
* Copyright 2019 NXP
*/
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
/*
* We use absolute address not PC relative address to jump.
* When running SPL on iMX8, the A core starts at address 0, a alias to OCRAM 0x100000,
void lpc32xx_i2c_init(unsigned int devnum);
void lpc32xx_ssp_init(void);
void lpc32xx_usb_init(void);
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
void ddr_init(const struct emc_dram_settings *dram);
#endif
#endif /* _LPC32XX_SYS_PROTO_H */
int litesom_mmc_init(struct bd_info *bis);
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void litesom_init_f(void);
#endif
#ifndef __ASM_ARCH_MX6_DDR_H__
#define __ASM_ARCH_MX6_DDR_H__
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#ifdef CONFIG_MX6Q
#include "mx6q-ddr.h"
#else
const struct mx6_mmdc_calibration *,
const void *);
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
#define MX6_MMDC_P0_MDCTL 0x021b0000
#define MX6_MMDC_P0_MDPDC 0x021b0004
int mxsmmc_initialize(struct bd_info *bis, int id, int (*wp)(int),
int (*cd)(int));
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#if defined(CONFIG_MX23)
#include <asm/arch/iomux-mx23.h>
* (containing the magic 'RK30'). This magic constant will be written into
* the final image by the rkimage tool, but we need to reserve space for it here.
*/
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
b 1f /* if overwritten, entry-address is at the next word */
1:
#endif
pop {r1-r12, pc}
#endif
-#if (defined(CONFIG_SPL_BUILD))
+#if (defined(CONFIG_XPL_BUILD))
/* U-Boot proper of armv7 does not need this */
b reset
#endif
* To make life easier for everyone, we build the SPL binary with
* space for this 4-byte header already included in the binary.
*/
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/*
* We need to add 4 bytes of space for the 'RK33' at the
* beginning of the executable. However, as we want to keep
.word 0
#endif
-#if (defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARM64))
+#if (defined(CONFIG_XPL_BUILD) || defined(CONFIG_ARM64))
/* U-Boot proper of armv7 do not need this */
b reset
#endif
ARM_VECTORS
#endif
-#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_SPL_BUILD) && \
+#if !defined(CONFIG_TPL_BUILD) && defined(CONFIG_XPL_BUILD) && \
(CONFIG_ROCKCHIP_SPL_RESERVE_IRAM > 0)
.space CONFIG_ROCKCHIP_SPL_RESERVE_IRAM /* space for the ATF data */
#endif
#define KHz 1000
#define OSC_HZ (24 * MHz)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
#define APLL_HZ (1008 * MHz)
#else
#define APLL_HZ (816 * MHz)
#define CPLL_HZ (500 * MHz)
#define HPLL_HZ (1400 * MHz)
#define PCLK_PDPMU_HZ (100 * MHz)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
#define ACLK_PDBUS_HZ (396 * MHz)
#else
#define ACLK_PDBUS_HZ (500 * MHz)
#define HCLK_PDCORE_HZ (200 * MHz)
#define HCLK_PDAUDIO_HZ (150 * MHz)
#define CLK_OSC0_DIV_HZ (32768)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
#define ACLK_PDVI_HZ (297 * MHz)
#define CLK_ISP_HZ (297 * MHz)
#define ACLK_PDISPP_HZ (297 * MHz)
DCLK_VOP_DIV_SHIFT = 0,
DCLK_VOP_DIV_MASK = 0xff,
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
/* CRU_CLK_SEL49_CON */
ACLK_PDVI_SEL_SHIFT = 6,
ACLK_PDVI_SEL_MASK = 0x3 << ACLK_PDVI_SEL_SHIFT,
CLK_GMAC_SRC_DIV_SHIFT = 0,
CLK_GMAC_SRC_DIV_MASK = 0x1f << CLK_GMAC_SRC_DIV_SHIFT,
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT)
/* CRU_CLK_SEL68_CON */
ACLK_PDISPP_SEL_SHIFT = 6,
ACLK_PDISPP_SEL_MASK = 0x3 << ACLK_PDISPP_SEL_SHIFT,
#include <asm/arch/cpu.h>
-#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_XPL_BUILD)
/* reserve space for BOOT0 header information */
b reset
.space 1532
.word CONFIG_SUNXI_RVBAR_ADDRESS // writable RVBAR mapping addr
.word SUNXI_SRAMC_BASE
.word CONFIG_SUNXI_RVBAR_ALTERNATIVE // address for die variant
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
.word CONFIG_SPL_TEXT_BASE
#else
.word CONFIG_TEXT_BASE
void return_to_fel(uint32_t lr, uint32_t sp);
/* Board / SoC level designware gmac init */
-#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC
+#if !defined CONFIG_XPL_BUILD && defined CONFIG_SUN7I_GMAC
void eth_init_board(void);
#else
static inline void eth_init_board(void) {}
#define __FSL_SECURE_BOOT_H
#ifdef CONFIG_CHAIN_OF_TRUST
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
-#endif /* #ifndef CONFIG_SPL_BUILD */
+#endif /* #ifndef CONFIG_XPL_BUILD */
#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
#endif
*/
static inline u32 omap_hw_init_context(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
return OMAP_INIT_CONTEXT_SPL;
#else
if (uboot_loaded_by_spl())
obj-y += setjmp.o
endif
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
ifdef CONFIG_ARM64
obj-y += relocate_64.o
else
#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
ldr r0, =(CONFIG_TPL_STACK)
-#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr r0, =(CONFIG_SPL_STACK)
#else
ldr r0, =(SYS_INIT_SP_ADDR)
bl debug_uart_init
#endif
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_EARLY_BSS)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_EARLY_BSS)
CLEAR_BSS
#endif
mov r0, #0
bl board_init_f
-#if ! defined(CONFIG_SPL_BUILD)
+#if ! defined(CONFIG_XPL_BUILD)
/*
* Set up intermediate environment (new sp and gd) and call
bl c_runtime_cpu_setup /* we still call old routine here */
#endif
-#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK)
+#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK)
-#if !defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_EARLY_BSS)
+#if !defined(CONFIG_XPL_BUILD) || !defined(CONFIG_SPL_EARLY_BSS)
CLEAR_BSS
#endif
-# ifdef CONFIG_SPL_BUILD
+# ifdef CONFIG_XPL_BUILD
/* Use a DRAM stack for the rest of SPL, if requested */
bl spl_relocate_stack_gd
cmp r0, #0
movne r9, r0
# endif
-#if ! defined(CONFIG_SPL_BUILD)
+#if ! defined(CONFIG_XPL_BUILD)
bl coloured_LED_init
bl red_led_on
#endif
*/
#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK)
ldr x0, =(CONFIG_TPL_STACK)
-#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+#elif defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
ldr x0, =(CONFIG_SPL_STACK)
#elif defined(CONFIG_INIT_SP_RELATIVE)
#if CONFIG_POSITION_INDEPENDENT
mov x0, #0
bl board_init_f
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
/*
* Set up intermediate environment (new sp and gd) and call
* relocate_code(addr_moni). Trick here is that we'll return
* Set up final (full) environment
*/
bl c_runtime_cpu_setup /* still call old routine */
-#endif /* !CONFIG_SPL_BUILD */
-#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK)
-#if defined(CONFIG_SPL_BUILD)
+#endif /* !CONFIG_XPL_BUILD */
+#if !defined(CONFIG_XPL_BUILD) || CONFIG_IS_ENABLED(FRAMEWORK)
+#if defined(CONFIG_XPL_BUILD)
bl spl_relocate_stack_gd /* may return NULL */
/* set up gd here, outside any C code, if new stack is returned */
cmp x0, #0
int raise (int signum)
{
/* Even if printf() is available, it's large. Punt it for SPL builds */
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
printf("raise: Signal # %d caught\n", signum);
#endif
return 0;
int arch_reserve_stacks(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */
gd->irq_sp = gd->start_addr_sp;
#else
/* SPL interrupt handling: just hang */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#if !CONFIG_IS_ENABLED(SYS_NO_VECTOR_TABLE)
.align 5
b 1b /* hang and never return */
#endif
-#else /* !CONFIG_SPL_BUILD */
+#else /* !CONFIG_XPL_BUILD */
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
bad_save_user_regs
bl do_fiq
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC &&
zi->zi_magic != BAREBOX_IMAGE_MAGIC) {
- if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ if (!IS_ENABLED(CONFIG_XPL_BUILD))
puts("zimage: Bad magic!\n");
return 1;
}
*start = zi->zi_start;
*end = zi->zi_end;
- if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ if (!IS_ENABLED(CONFIG_XPL_BUILD))
printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n",
image, *start, *end);
obj-y += lowlevel_init.o board_common.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
.globl lowlevel_init
lowlevel_init:
-#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL) && !defined(CONFIG_XPL_BUILD)
mov pc, lr
#else
/* setup ARM arch timer frequency */
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
-ifneq ($(CONFIG_SPL_BUILD),)
+ifneq ($(CONFIG_XPL_BUILD),)
obj-$(CONFIG_AT91SAM9260) += sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o
obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
endif
ifeq ($(CONFIG_CPU_V7A),y)
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
INPUTS-y += u-boot.img
endif
endif
obj-$(CONFIG_DA850_LOWLEVEL) += da850_lowlevel.o
obj-$(CONFIG_SOC_DA850) += da850_pinmux.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_FRAMEWORK) += spl.o
obj-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
endif
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2012, Texas Instruments, Incorporated - https://www.ti.com/
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
INPUTS-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais
endif
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
obj-$(CONFIG_EXYNOS5420) += sec_boot.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_ARCH_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_ARCH_EXYNOS5) += dmc_common.o dmc_init_ddr3.o
obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o
if (actions & DO_CLOCKS) {
system_clock_init();
#ifdef CONFIG_DEBUG_UART
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \
- !defined(CONFIG_SPL_BUILD)
+#if (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \
+ !defined(CONFIG_XPL_BUILD)
exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
debug_uart_init();
#endif
* this same assumption.
*/
if ((peripheral == PERIPH_ID_SDMMC0) && (i == (start + 2))) {
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
gpio_request(i, "sdmmc0_vdden");
#endif
gpio_set_value(i, 1);
endif
ifeq ($(SOC),$(filter $(SOC),imx8m))
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
endif
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
endif
ifeq ($(SOC),$(filter $(SOC),imx8m imx9))
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
obj-y += fdt.o
endif
endif
ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imx9 imxrt))
obj-y += misc.o
obj-$(CONFIG_CMD_PRIBLOB) += priblob.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
endif
ifeq ($(SOC),$(filter $(SOC),mx7))
obj-y += cpu.o
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
endif
ifeq ($(SOC),$(filter $(SOC),mx7 imx8m))
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o
endif
endif
obj-y += cache.o init.o
obj-$(CONFIG_FEC_MXC) += mac.o
obj-$(CONFIG_IMX_RDC) += rdc-sema.o
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
endif
obj-$(CONFIG_$(SPL_)SATA) += sata.o
obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o
endif
ifeq ($(SOC),$(filter $(SOC),imx8))
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
endif
endif
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o
endif
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image-container.o
endif
ifeq ($(CONFIG_ARCH_IMX8), y)
CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh
IMAGE_TYPE := imx8image
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
SPL_DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG); if [ -f spl/u-boot-spl.cfgout ]; then $(CNTR_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi)
endif
DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
if (reset_cause == -1) {
reset_cause = readl(&src_regs->srsr);
/* preserve the value for U-Boot proper */
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
writel(reset_cause, &src_regs->srsr);
#endif
}
return reset_cause;
}
-#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD)
static char *get_reset_cause(void)
{
switch (get_imx_reset_cause()) {
}
#endif
-#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD)
const char *get_imx_type(u32 imxtype)
{
return ret;
}
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
#define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
""
);
-#endif /* !defined(CONFIG_SPL_BUILD) */
+#endif /* !defined(CONFIG_XPL_BUILD) */
/* Get CSF Header length */
static int get_hab_hdr_len(struct hab_hdr *hdr)
puts("Dumping CSF Header\n");
print_buffer(ivt->csf, (void *)(uintptr_t)(ivt->csf), 4, 0x10, 0);
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
get_hab_status();
#endif
}
hab_exit_failure_print_status:
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
get_hab_status();
#endif
int arch_cpu_init(void)
{
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
spl_save_restore_data();
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
struct pass_over_info_t *pass_over;
if (is_soc_rev(CHIP_REV_A)) {
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void dram_pll_init(ulong pll_val)
{
u32 val;
/*
* Dump some clockes.
*/
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int timer_init(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
unsigned long freq = readl(&sctr->cntfid0);
return ret;
/* rom_pointer[1] contains the size of TEE occupies */
- if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1])
+ if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1])
gd->ram_size = sdram_size - rom_pointer[1];
else
gd->ram_size = sdram_size;
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
- if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
+ if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
sdram_b1_size = sdram_size;
}
- if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) &&
+ if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_XPL_BUILD) &&
rom_pointer[1]) {
/* We will relocate u-boot to Top of dram1. Tee position has two cases:
* 1. At the top of dram1, Then return the size removed optee size.
phys_size_t sdram_size;
int entry, ret;
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
return;
if (CONFIG_IS_ENABLED(SYS_ICACHE_OFF) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
* ROM might disable clock for SCTR,
* enable the clock before timer_init.
*/
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
clock_enable(CCGR_SCTR, 1);
/*
* Init timer at very early state, because sscg pll setting
*/
timer_init();
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
clock_init();
imx_set_wdog_powerdown(false);
}
#endif
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
#if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
bool serror_need_skip = true;
obj-y += lowlevel_init.o
obj-y += soc.o clock.o iomux.o pcc.o cgc.o rdc.o
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
obj-y += upower/
endif
return pcc_clock_get_rate(lpuart_pcc[index], lpuart_pcc_slots[index]);
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/*
* Dump some core clockes.
*/
.global save_boot_params
save_boot_params:
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* The firmware provided ATAG/FDT address can be found in r2/x0 */
adr x0, rom_pointer
stp x1, x2, [x0], #16
bool m33_image_booted(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
u32 gp6 = 0;
/* DGO_GP6 */
bool rdc_enabled_in_boot(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
u32 val = 0;
int ret;
bool rdc_en = true; /* Default assume DBD_EN is set */
static void spl_pass_boot_info(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
bool m33_booted = m33_image_booted();
bool rdc_en = rdc_enabled_in_boot();
u32 val = 0;
bool is_m33_handshake_necessary(void)
{
/* Only need handshake in u-boot */
- if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ if (!IS_ENABLED(CONFIG_XPL_BUILD))
return (m33_image_booted() || rdc_enabled_in_boot());
else
return false;
int arch_cpu_init(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
/* Enable System Reset Interrupt using WDOG_AD */
setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13));
/* Clear AD_PERIPH Power switch domain out of reset interrupt flag */
}
EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8ulp_dm_post_init);
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
debug("image entry point: 0x%lx\n", spl_image->entry_point);
obj-y += lowlevel_init.o
obj-y += soc.o clock.o clock_root.o trdc.o
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
obj-y += imx_bootaux.o
#endif
}
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void dram_pll_init(ulong pll_val)
{
configure_fracpll(DRAM_PLL_CLK, pll_val);
/*
* Dump some clockes.
*/
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
{
u32 freq;
.global save_boot_params
save_boot_params:
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* The firmware provided ATAG/FDT address can be found in r2/x0 */
adr x0, rom_pointer
stp x1, x2, [x0], #16
return ret;
/* rom_pointer[1] contains the size of TEE occupies */
- if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1])
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1])
gd->ram_size = sdram_size - rom_pointer[1];
else
gd->ram_size = sdram_size;
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
- if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
else
sdram_b1_size = sdram_size;
- if (!IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) && rom_pointer[1]) {
/* We will relocate u-boot to top of dram1. TEE position has two cases:
* 1. At the top of dram1, Then return the size removed optee size.
* 2. In the middle of dram1, return the size of dram1.
}
#ifdef CONFIG_OF_BOARD_FIXUP
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int board_fix_fdt(void *fdt)
{
/* Update dtb clocks for low drive mode */
int arch_cpu_init(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
/* Disable wdog */
init_wdog();
int timer_init(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
unsigned long freq = readl(&sctr->cntfid0);
}
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/*
* Dump some core clockes.
*/
obj-y := soc.o clock.o
obj-$(CONFIG_IMX_MODULE_FUSE) += module_fuse.o
-obj-$(CONFIG_SPL_BUILD) += ddr.o
+obj-$(CONFIG_XPL_BUILD) += ddr.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_MX6UL_LITESOM) += litesom.o
obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o
}
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/*
* Dump some core clockes.
*/
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <linux/libfdt.h>
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#include <asm/arch/mx6-ddr.h>
#include <linux/libfdt.h>
#include <spl.h>
/* DDR initialization */
spl_dram_init();
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
u32 fpga_rev;
};
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX_THERMAL)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_IMX_THERMAL)
static const struct imx_thermal_plat imx6_thermal_plat = {
.regs = (void *)ANATOP_BASE_ADDR,
.fuse_bank = 1,
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/*
* cfg_val will be used for
* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
void reset_misc(void)
{
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO)
lcdif_power_down();
#endif
}
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/*
* Dump some core clockes.
*/
return;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
const struct boot_mode soc_boot_modes[] = {
{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
{"primary", MAKE_CFGVAL_PRIMARY_BOOT},
void reset_misc(void)
{
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_VIDEO)
lcdif_power_down();
#endif
}
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/*
* Dump some core clockes.
*/
return false;
}
-#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
+#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_XPL_BUILD))
#if defined(CONFIG_LDO_ENABLED_MODE)
static void init_ldo_mode(void)
{
return usec;
}
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || IS_ENABLED(CONFIG_SPL_BUILD)
+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || IS_ENABLED(CONFIG_XPL_BUILD)
int timer_init(void)
{
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
# Andrew Davis <afd@ti.com>
obj-$(CONFIG_OF_SYSTEM_SETUP) += am62a7_fdt.o
-obj-$(CONFIG_SPL_BUILD) += am62a7_init.o
+obj-$(CONFIG_XPL_BUILD) += am62a7_init.o
# Andrew Davis <afd@ti.com>
obj-$(CONFIG_OF_SYSTEM_SETUP) += am62p5_fdt.o
-obj-$(CONFIG_SPL_BUILD) += am62p5_init.o
+obj-$(CONFIG_XPL_BUILD) += am62p5_init.o
# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_OF_SYSTEM_SETUP) += am625_fdt.o
-obj-$(CONFIG_SPL_BUILD) += am625_init.o
+obj-$(CONFIG_XPL_BUILD) += am625_init.o
obj-y += boot.o
# SPDX-License-Identifier: GPL-2.0+
-obj-$(CONFIG_SPL_BUILD) += am642_init.o
+obj-$(CONFIG_XPL_BUILD) += am642_init.o
obj-y += boot.o
# Andrew Davis <afd@ti.com>
obj-$(CONFIG_OF_SYSTEM_SETUP) += am654_fdt.o
-obj-$(CONFIG_SPL_BUILD) += am654_init.o
+obj-$(CONFIG_XPL_BUILD) += am654_init.o
#include <config.h>
#include <linux/linkage.h>
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
ENTRY(__asm_invalidate_l3_dcache)
/* Invalidate SPL address range */
mov x0, #CONFIG_SPL_TEXT_BASE
# Andrew Davis <afd@ti.com>
obj-$(CONFIG_OF_SYSTEM_SETUP) += j721e_fdt.o
-obj-$(CONFIG_SPL_BUILD) += j721e_init.o
+obj-$(CONFIG_XPL_BUILD) += j721e_init.o
# Andrew Davis <afd@ti.com>
obj-$(CONFIG_OF_SYSTEM_SETUP) += j721s2_fdt.o
-obj-$(CONFIG_SPL_BUILD) += j721s2_init.o
+obj-$(CONFIG_XPL_BUILD) += j721s2_init.o
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void board_init_f(ulong dummy)
{
k3_spl_init();
# Jayesh Choudhary <j-choudhary@ti.com>
obj-$(CONFIG_OF_SYSTEM_SETUP) += j722s_fdt.o
-obj-$(CONFIG_SPL_BUILD) += j722s_init.o
+obj-$(CONFIG_XPL_BUILD) += j722s_init.o
# Andrew Davis <afd@ti.com>
obj-$(CONFIG_OF_SYSTEM_SETUP) += j784s4_fdt.o
-obj-$(CONFIG_SPL_BUILD) += j784s4_init.o
+obj-$(CONFIG_XPL_BUILD) += j784s4_init.o
obj-y += lowlevel_init.o
obj-y += r5_mpu.o
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
endif
* via YMODEM. This is done to avoid disturbing the YMODEM serial
* protocol transactions.
*/
- if (!(IS_ENABLED(CONFIG_SPL_BUILD) &&
+ if (!(IS_ENABLED(CONFIG_XPL_BUILD) &&
IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) &&
spl_boot_device() == BOOT_DEVICE_UART))
printf("Authentication passed\n");
obj-y += clock.o
obj-y += mon.o
CFLAGS_REMOVE_mon.o := $(LTO_CFLAGS)
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += cmd_poweroff.o
include $(srctree)/arch/arm/mach-omap2/config_secure.mk
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
INPUTS-y += u-boot_HS_MLO
else
u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE
$(call if_changed,pad_cat)
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
MKIMAGEFLAGS_MLO = -A $(ARCH) -T gpimage -C none \
-a $(CONFIG_TEXT_BASE) -e $(CONFIG_TEXT_BASE) -n U-Boot
MLO: u-boot.bin FORCE
* via YMODEM. This is done to avoid disturbing the YMODEM serial
* protocol transactions.
*/
- if (!(IS_ENABLED(CONFIG_SPL_BUILD) &&
+ if (!(IS_ENABLED(CONFIG_XPL_BUILD) &&
IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) &&
spl_boot_device() == BOOT_DEVICE_UART))
printf("Authentication passed\n");
obj-y = cpu.o clk.o devices.o timer.o
-obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o
+obj-$(CONFIG_XPL_BUILD) += dram.o lowlevel_init.o
# SPDX-License-Identifier: GPL-2.0
obj-y += cpu.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
obj-$(CONFIG_MT8512) += mt8512/
obj-$(CONFIG_TARGET_MT7622) += mt7622/
ENTRY(lowlevel_init)
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* Return to U-Boot via saved link register */
mov pc, lr
#else
obj-y = cpu.o
obj-y += dram.o
obj-y += lowlevel.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
include/config/auto.conf
$(call cmd,kwbcfg)
-endif # CONFIG_SPL_BUILD
+endif # CONFIG_XPL_BUILD
obj-y += gpio.o
obj-y += mbus.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
-obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += lowlevel_spl.o
obj-$(CONFIG_ARMADA_38X) += serdes/a38x/
obj-$(CONFIG_ARMADA_XP) += serdes/axp/
*/
}
-#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)
+#if defined(CONFIG_XPL_BUILD) || !defined(CONFIG_ARMADA_32BIT_SYSCON_SYSRESET)
void reset_cpu(void)
{
struct mvebu_system_registers *reg =
int i;
/* mbus is not initialized in SPL; keep the ROM settings */
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
return;
dram = mvebu_mbus_dram_info();
/*
* Default Device Address MAP BAR values
*/
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#ifdef CONFIG_ARMADA_38X
#define MBUS_PCI_MEM_BASE 0x88000000
#define MBUS_PCI_MEM_SIZE ((3 * 128) << 20)
#define MBUS_PCI_IO_BASE 0xF1100000
#define MBUS_PCI_IO_SIZE ((MBUS_PCI_MAX_PORTS * 64) << 10)
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#define MBUS_SPI_BASE 0xD4000000
#define MBUS_SPI_SIZE (64 << 20)
#else
#define MBUS_SPI_BASE 0xF4000000
#define MBUS_SPI_SIZE (8 << 20)
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#define MBUS_DFX_BASE 0xF6000000
#define MBUS_DFX_SIZE (1 << 20)
#endif
#define MBUS_BOOTROM_BASE 0xF8000000
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#define MBUS_BOOTROM_SIZE (128 << 20)
#else
#define MBUS_BOOTROM_SIZE (8 << 20)
/* SOC specific definations */
#define INTREG_BASE 0xd0000000
#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
-#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_ARMADA_3700)
+#if defined(CONFIG_XPL_BUILD) || defined(CONFIG_ARMADA_3700)
/*
* The SPL U-Boot version still runs with the default
* address for the internal registers, configured by
# SPDX-License-Identifier: GPL-2.0+
-obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o
-obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec-38x.o
-obj-$(CONFIG_SPL_BUILD) += seq_exec.o
-obj-$(CONFIG_SPL_BUILD) += sys_env_lib.o
+obj-$(CONFIG_XPL_BUILD) += high_speed_env_spec.o
+obj-$(CONFIG_XPL_BUILD) += high_speed_env_spec-38x.o
+obj-$(CONFIG_XPL_BUILD) += seq_exec.o
+obj-$(CONFIG_XPL_BUILD) += sys_env_lib.o
# SPDX-License-Identifier: GPL-2.0+
-obj-$(CONFIG_SPL_BUILD) = high_speed_env_lib.o
-obj-$(CONFIG_SPL_BUILD) += high_speed_env_spec.o
+obj-$(CONFIG_XPL_BUILD) = high_speed_env_lib.o
+obj-$(CONFIG_XPL_BUILD) += high_speed_env_spec.o
int dp_plane_set_address(int module, int layer, unsigned int address);
int dp_plane_wait_vsync(int module, int layer, int fps);
-#if defined CONFIG_SPL_BUILD || \
+#if defined CONFIG_XPL_BUILD || \
(!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL))
int nx_display_probe(struct nx_display_plat *plat);
#endif
ifeq ($(CONFIG_TIMER),)
obj-y += timer.o
else
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += timer.o
endif
endif
/* AM33XX has two MUSB controllers which can be host or gadget */
#if (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
- defined(CONFIG_SPL_BUILD)
+ defined(CONFIG_XPL_BUILD)
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
- (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
+ (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
static void rtc32k_unlock(struct davinci_rtc *rtc)
{
/*
}
#endif
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
/*
* Write contents of the RTC_SCRATCH1 register based on board type
* Two things are passed
{
set_mux_conf_regs();
prcm_init();
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
update_rtc_magic();
#endif
return 0;
;
}
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
/*
* Check if we are executing rtc-only + DDR mode, and resume from it if needed
*/
void s_init(void)
{
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
rtc_only();
#endif
}
set_uart_mux_conf();
setup_early_clocks();
uart_soft_reset();
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
save_omap_boot_params();
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
spl_early_init();
#endif
#endif
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void board_init_f(ulong dummy)
{
hw_data_init();
#endif
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
u32 spl_boot_device(void)
{
return gd->arch.omap_boot_device;
int ret, size;
u32 loadaddr = IPU1_LOAD_ADDR;
- if (!IS_ENABLED(CONFIG_SPL_BUILD) ||
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) ||
!IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
return;
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
hw_watchdog_init();
#endif
- if (IS_ENABLED(CONFIG_SPL_BUILD) &&
+ if (IS_ENABLED(CONFIG_XPL_BUILD) &&
IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
spl_boot_ipu();
}
#include <asm/omap_gpio.h>
#include <asm/emif.h>
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/*
* printing to console doesn't work unless
* this code is executed from SPL
include $(srctree)/arch/arm/mach-omap2/config_secure.mk
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifeq ($(CONFIG_TI_SECURE_DEVICE),y) # Refer to README.ti-secure for more info
# On DRA7xx/AM57xx:
#
quiet_cmd_mkomapsecimg = SECURE $@
ifneq ($(TI_SECURE_DEV_PKG),)
ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
-ifneq ($(CONFIG_SPL_BUILD),)
+ifneq ($(CONFIG_XPL_BUILD),)
cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
$(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_SPL_TEXT_BASE) \
$(if $(KBUILD_VERBOSE:1=), >/dev/null)
puts("\n");
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void spl_display_print(void)
{
omap_rev_string();
*/
int early_system_init(void)
{
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
int ret;
int rescan;
#endif
hw_data_init();
init_package_revision();
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
if (warm_reset())
force_emif_self_refresh();
#endif
watchdog_init();
set_mux_conf_regs();
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
srcomp_enable();
do_io_settings();
#endif
setup_early_clocks();
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
#endif
do_board_detect();
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
/*
* Board detection has been done.
* Let us see if another dtb wouldn't be a better match
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void board_init_f(ulong dummy)
{
early_system_init();
obj-y += sys_info.o
obj-y += prcm-regs.o
obj-y += hw_data.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o
endif
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void board_init_f(ulong dummy)
{
early_system_init();
{
}
-#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_XPL_BUILD)
/******************************************************************************
* OMAP3 specific command to switch between NAND HW and SW ecc
*****************************************************************************/
"nandecc sw - Switch to NAND software ecc algorithm."
);
-#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
+#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_XPL_BUILD */
#ifdef CONFIG_DISPLAY_BOARDINFO
/**
* then set cs_cfg to the appropriate value then try and
* setup CS1.
*/
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* set/modify board-specific timings */
get_board_mem_timings(&timings);
#endif
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
make_cs1_contiguous();
write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
writel(pad->val, base + pad->offset);
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
* via YMODEM. This is done to avoid disturbing the YMODEM serial
* protocol transactions.
*/
- if (!(IS_ENABLED(CONFIG_SPL_BUILD) &&
+ if (!(IS_ENABLED(CONFIG_XPL_BUILD) &&
IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) &&
spl_boot_device() == BOOT_DEVICE_UART))
printf("Authentication passed\n");
/* Enable and invalidate L2 cache in write through mode */
invalidate_l2_cache();
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
orion5x_config_adr_windows();
#endif
lowlevel_init:
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* Use 'r2 as the base for internal register accesses */
ldr r2, =ORION5X_REGS_PHY_BASE
ldr r0, =0x7fff0001
str r0, [r3, #0x504]
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
/* Return to U-Boot via saved link register */
mov pc, lr
_start:
ARM_VECTORS
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
.word 0x0badc0d3;
.word 0x0badc0d3;
.word 0x0badc0d3;
#include <system-constants.h>
ENTRY(lowlevel_init)
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
mrc p15, 0, r4, c0, c0, 5 /* mpidr */
orr r4, r4, r4, lsr #6
and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
+ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
# Always include boot_mode.o, as we bypass it (i.e. turn it off)
# inside of boot_mode.c when CONFIG_ROCKCHIP_BOOT_MODE_REG is 0. This way,
obj-spl-$(CONFIG_TPL_BUILD) =
# Now add SPL/TPL objects back into the main build
-obj-$(CONFIG_SPL_BUILD) += $(obj-spl-y)
+obj-$(CONFIG_XPL_BUILD) += $(obj-spl-y)
obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y)
static struct px30_cru * const cru = (void *)CRU_BASE;
u32 __maybe_unused val;
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* We do some SoC one time setting here. */
/* Disable the ddr secure region setting to make it non-secure */
writel(0x0, DDR_FW_BASE + FW_DDR_CON);
obj-y += clk_rk3036.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += syscon_rk3036.o
endif
void spl_board_init(void)
{
- if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ if (!IS_ENABLED(CONFIG_XPL_BUILD))
return;
if (IS_ENABLED(CONFIG_SPL_DM_MMC)) {
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
int arch_cpu_init(void)
{
struct rk3188_grf *grf;
return rk3188_board_late_init();
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static int setup_led(void)
{
#ifdef CONFIG_SPL_LED
int arch_cpu_init(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#define SGRF_BASE 0x10150000
static struct rk322x_sgrf * const sgrf = (void *)SGRF_BASE;
[BROM_BOOTSOURCE_SD] = "/mmc@ff0c0000",
};
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static void configure_l2ctlr(void)
{
u32 l2ctlr;
int arch_cpu_init(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
configure_l2ctlr();
#else
/* We do some SoC one time setting here. */
}
#endif
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
int arch_cpu_init(void)
{
static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE;
int arch_cpu_init(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
u32 reg;
/* We do some SoC one time setting here. */
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/*
* The SPL (and also the full U-Boot stage on the RK3368) will run in
* secure mode (i.e. EL3) and an ATF will eventually be booted before
struct mm_region *mem_map = rk3399_mem_map;
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#define TIMER_END_COUNT_L 0x00
#define TIMER_END_COUNT_H 0x04
int arch_cpu_init(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
struct rk3399_pmusgrf_regs *sgrf;
struct rk3399_grf_regs *grf;
struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
- if (IS_ENABLED(CONFIG_SPL_BUILD) &&
+ if (IS_ENABLED(CONFIG_XPL_BUILD) &&
(IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_BOB) ||
IS_ENABLED(CONFIG_TARGET_CHROMEBOOK_KEVIN))) {
rk_setreg(&grf->io_vsel, 1 << 0);
}
#endif
-#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+#if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD)
static void rk3399_force_power_on_reset(void)
{
ofnode node;
int arch_cpu_init(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/*
* When perform idle operation, corresponding clock can
* be opened or gated automatically.
GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void rockchip_stimer_init(void)
{
/* If Timer already enabled, don't re-init it */
#ifndef CONFIG_TPL_BUILD
int arch_cpu_init(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#ifdef CONFIG_ROCKCHIP_DISABLE_FORCE_JTAG
static struct rk3588_sysgrf * const sys_grf = (void *)SYS_GRF_BASE;
#endif
# SPDX-License-Identifier: GPL-2.0+
#
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += syscon_rv1108.o
endif
obj-y += rv1108.o
* since they are unsecure.
* (Note: only secure-world can access this register)
*/
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
writel(0, FIREWALL_APB_BASE + FW_DDR_CON_REG);
return 0;
obj-$(CONFIG_SC59X) += sc59x.o
obj-$(CONFIG_SC59X_64) += sc59x_64.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
obj-$(CONFIG_SYSCON) += rcu.o
# Contact: Greg Malysa <greg.malysa@timesys.com>
#
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
INPUTS-y += $(obj)/u-boot-spl.ldr
endif
obj-y += wrap_pll_config_soc64.o
endif
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
obj-y += freeze_controller.o
u32 jtag_usercode;
int err;
-#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)
+#if !IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)
err = smc_get_usercode(&jtag_usercode);
#else
u32 resp_len = 1;
return board_id;
}
-#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
int board_fit_config_name_match(const char *name)
{
char board_name[10];
}
#endif
-#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
+#if !IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_FIT)
void board_prep_linux(struct bootm_headers *images)
{
bool use_fit = false;
}
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
#include <asm/arch/clock_manager.h>
#include <linux/delay.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void sdelay(unsigned long loops);
u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
_start:
ARM_VECTORS
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
.balignl 64,0xf33db33f;
.word 0x1337c0d3; /* SoCFPGA preloader validation word */
#define CLKMGR_INTER CLKMGR_A10_INTER
#define CLKMGR_PERPLL_EN CLKMGR_A10_PERPLL_EN
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
int cm_basic_init(const void *blob);
#endif
mov x29, lr /* Save LR */
#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
wait_for_atf:
ldr x4, =CPU_RELEASE_ADDR
ldr x5, [x4]
int mbox_reset_cold(void)
{
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
psci_system_reset();
#else
int ret;
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
},
};
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CFG_SYS_PL310_BASE;
static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
void socfpga_bridges_reset(int enable)
{
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+#if !defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
u64 arg = enable;
int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
debug("mbox_relocate_data_addr = 0x%p\n", mbox_relocate_data_addr);
do {
- if (!IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) {
+ if (!IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)) {
/* Invoke SMC call to ATF to send the VAB certificate to SDM */
ret = smc_send_mailbox(MBOX_VAB_SRC_CERT, mbox_data_sz,
(u32 *)mbox_relocate_data_addr, 0, &resp_len,
*/
int timer_init(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
int enable = 0x3; /* timer enable + output signal masked */
int loadval = ~0;
while (__get_time_stamp() < tmp + 1) /* loop till event */
;
-}
\ No newline at end of file
+}
const struct cm_config * const cm_get_default_config(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
struct cm_config *cm_handoff_cfg = (struct cm_config *)
(SOC64_HANDOFF_CLOCK + SOC64_HANDOFF_OFFSET_DATA);
u32 *conversion = (u32 *)cm_handoff_cfg;
const unsigned int cm_get_osc_clk_hz(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
u32 clock = readl(SOC64_HANDOFF_CLOCK_OSC);
const unsigned int cm_get_fpga_clk_hz(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
u32 clock = readl(SOC64_HANDOFF_CLOCK_FPGA);
writel(clock,
obj-$(CONFIG_STM32MP25X) += stm32mp2/
obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += cmd_stm32prog/
obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o
obj-$(CONFIG_TFABOOT) += boot_params.o
u32 tmp_data = 0;
int ret;
- if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD))
return stm32_smc(STM32_SMC_BSEC,
STM32_SMC_READ_OTP,
otp, 0, val);
{
struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD))
return stm32_smc(STM32_SMC_BSEC,
STM32_SMC_READ_SHADOW,
otp, 0, val);
{
struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_PROG_OTP,
otp, val);
{
struct stm32mp_bsec_plat *plat;
- if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_WRITE_SHADOW,
otp, val);
return 0; /* nothing to do */
}
- if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_XPL_BUILD))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_WRLOCK_OTP,
otp, 0);
* update unlocked shadow for OTP cleared by the rom code
* only executed in SPL, it is done in TF-A for TFABOOT
*/
- if (IS_ENABLED(CONFIG_SPL_BUILD) && !data->ta) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD) && !data->ta) {
plat = dev_get_plat(dev);
/* here 57 is the value for STM32MP15x ROM code, only MPU with SPL support*/
obj-$(CONFIG_STM32MP13X) += stm32mp13x.o
obj-$(CONFIG_STM32MP15X) += stm32mp15x.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-y += tzc400.o
else
bool use_lmb = false;
enum dcache_option option;
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
/* STM32_SYSRAM_BASE exist only when SPL is supported */
#ifdef CONFIG_SPL
start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
(boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
- else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD))
+ else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_XPL_BUILD))
debug_uart_init();
return 0;
return nt_fw_dtb;
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
typedef void __noreturn (*image_entry_stm32_t)(u32 romapi);
/* weak function: STM32MP15x mach init for boot without TFA */
void stm32mp_cpu_init(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD)) {
security_init();
update_bootmode();
}
/* reset copro state in SPL, when used, or in U-Boot */
- if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_XPL_BUILD)) {
/* Reset Coprocessor state unless it wakes up from Standby power mode */
if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
obj-y += timer.o
endif
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += clock.o
obj-$(CONFIG_MACH_SUNIV) += dram_suniv.o
obj-$(CONFIG_DRAM_SUN4I) += dram_sun4i.o
}
#endif /* CONFIG_ARM64 */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static int gpio_init(void)
{
__maybe_unused uint val;
return 0;
}
SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
#define SUNXI_INVALID_BOOT_SOURCE -1
* proper, just return MMC0 as a placeholder, for now.
*/
if (IS_ENABLED(CONFIG_MACH_SUNIV) &&
- !IS_ENABLED(CONFIG_SPL_BUILD))
+ !IS_ENABLED(CONFIG_XPL_BUILD))
return SUNXI_BOOTED_FROM_MMC0;
if (IS_ENABLED(CONFIG_MACH_SUNIV))
return -1; /* Never reached */
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
uint32_t sunxi_get_spl_size(void)
{
struct boot_file_head *egon_head = (void *)SPL_ADDR;
#endif
sunxi_board_init();
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void clock_init_safe(void)
{
struct sunxi_ccm_reg * const ccm =
&ccm->cpu_ahb_apb0_cfg);
sdelay(20);
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
/* video, DRAM, PLL_PERIPH clocks */
void clock_set_pll3(unsigned int clk)
#include <asm/arch/clock.h>
#include <asm/arch/prcm.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void clock_init_safe(void)
{
struct sunxi_ccm_reg *const ccm =
return 0;
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
/* PLL_PERIPH0 clock, used by the MMC driver */
unsigned int clock_get_pll6(void)
#include <linux/bitops.h>
#include <linux/delay.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void clock_init_safe(void)
{
struct sunxi_ccm_reg * const ccm =
&ccm->cpu_axi_cfg);
}
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
/* video, DRAM, PLL_PERIPH clocks */
void clock_set_pll3(unsigned int clk)
#include <asm/arch/sys_proto.h>
#include <linux/delay.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void clock_init_safe(void)
{
struct sunxi_ccm_reg * const ccm =
CPU_CLK_SRC_PLL1 << C1_CPUX_CLK_SRC_SHIFT,
&ccm->cpu_axi_cfg);
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
/* DRAM and PLL_PERIPH0 clock (used by the MMC driver) */
void clock_set_pll5(unsigned int clk)
#include <asm/arch/prcm.h>
#include <asm/arch/sys_proto.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
static void clock_set_pll2(unsigned int clk)
{
return 0;
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
/* PLL_PERIPH0 clock (used by the MMC driver) */
unsigned int clock_get_pll4_periph0(void)
#include <asm/arch/gtbus_sun9i.h>
#include <asm/arch/sys_proto.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void gtbus_init(void)
{
# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += spl.o
obj-y += cpu.o
else
obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
obj-$(CONFIG_TEGRA_GPU) += gpu.o
obj-$(CONFIG_TEGRA_IVC) += ivc.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_ARMV7_PSCI) += psci.o
endif
obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
static bool from_spl __section(".data");
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
unsigned long r3)
{
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
U_BOOT_DRVINFO(tegra_gpios) = {
"gpio_tegra"
#
# Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
-obj-$(CONFIG_SPL_BUILD) += cpu.o
+obj-$(CONFIG_XPL_BUILD) += cpu.o
obj-y += clock.o
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_SPL_BUILD) += cpu.o
+obj-$(CONFIG_XPL_BUILD) += cpu.o
obj-y += clock.o
obj-y += pmc.o
obj-y += xusb-padctl.o
obj-y += ../xusb-padctl-common.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_ARMV7_NONSEC) += psci.o
endif
#
# (C) Copyright 2010,2011 Nvidia Corporation.
-obj-$(CONFIG_SPL_BUILD) += cpu.o
+obj-$(CONFIG_XPL_BUILD) += cpu.o
obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o
# The AVP is ARMv4T architecture so we must use special compiler
#
# Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
-obj-$(CONFIG_SPL_BUILD) += cpu.o
+obj-$(CONFIG_XPL_BUILD) += cpu.o
obj-$(CONFIG_$(SPL_)CMD_EBTUPDATE) += bct.o
obj-y += clock.o
# SPDX-License-Identifier: GPL-2.0+
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += boards.o
obj-y += spl_board_init.o
# SPDX-License-Identifier: GPL-2.0+
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += lowlevel_init.o
obj-$(CONFIG_DEBUG_LL) += debug_ll.o
else
return !!(readl(sg_base + SG_PINMON0) & BIT(27));
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int do_pinmon(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
""
);
-#endif /* !CONFIG_SPL_BUILD */
+#endif /* !CONFIG_XPL_BUILD */
# SPDX-License-Identifier: GPL-2.0+
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
# SPDX-License-Identifier: GPL-2.0+
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += debug-uart-ld4.o
obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += debug-uart-pro4.o
obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += debug-uart-sld8.o
writel(c, base + UNIPHIER_UART_TX);
}
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void sg_set_pinsel(unsigned int pin, unsigned int muxval,
unsigned int mux_bits, unsigned int reg_stride)
{
void _debug_uart_init(void)
{
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE);
unsigned int divisor;
# SPDX-License-Identifier: GPL-2.0+
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_ARCH_UNIPHIER_LD4) += umc-ld4.o \
ddrphy-training.o ddrphy-ld4.o
obj-y += clk.o
obj-y += lowlevel_init.o
AFLAGS_lowlevel_init.o := -mfpu=neon
-obj-$(CONFIG_SPL_BUILD) += spl.o ps7_spl_init.o
+obj-$(CONFIG_XPL_BUILD) += spl.o ps7_spl_init.o
int arch_cpu_init(void)
{
zynq_slcr_unlock();
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
/* Device config APB, unlock the PCAP */
writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
obj-y += aes.o clk.o cpu.o
obj-$(CONFIG_MP) += mp.o
-obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o psu_spl_init.o
+obj-$(CONFIG_XPL_BUILD) += spl.o handoff.o psu_spl_init.o
obj-$(CONFIG_SPL_ZYNQMP_DRAM_ECC_INIT) += ecc_spl_init.o
obj-$(CONFIG_$(SPL_)ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_CMD_ZYNQMP) += zynqmp.o
-endif # !CONFIG_SPL_BUILD
+endif # !CONFIG_XPL_BUILD
const u32 mask,
const u32 value)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
+ if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3)
return zynqmp_mmio_rawwrite(address, mask, value);
#if defined(CONFIG_ZYNQMP_FIRMWARE)
else
if (!value)
return ret;
- if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
+ if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) {
ret = zynqmp_mmio_rawread(address, value);
}
#if defined(CONFIG_ZYNQMP_FIRMWARE)
LDFLAGS_FINAL += --gc-sections
-ifeq ($(CONFIG_SPL_BUILD),)
+ifeq ($(CONFIG_XPL_BUILD),)
PLATFORM_CPPFLAGS += -fPIC
LDFLAGS_u-boot += -pic
endif
obj-y = irq.o
obj-y += interrupts.o cache.o exception.o cpuinfo.o relocate.o
obj-$(CONFIG_XILINX_MICROBLAZE0_PVR) += pvr.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
mts rslr, r0
mts rshr, r20
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
addi r1, r0, CONFIG_SPL_STACK
#else
add r1, r0, r20
brlid r15, board_init_f_init_reserve
nop
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
/* Setup vectors with pre-relocation symbols */
or r5, r0, r0
brlid r15, __setup_exceptions
brlid r15, debug_uart_init
nop
#endif
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
or r5, r0, r0 /* flags - empty */
bri board_init_f
#else
#endif
1: bri 1b
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
.text
.ent __setup_exceptions
.align 2
head-y := arch/mips/cpu/start.o
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
head-$(CONFIG_ARCH_JZ47XX) := arch/mips/mach-jz47xx/start.o
head-$(CONFIG_SOC_MT7621) := arch/mips/mach-mtmips/mt7621/spl/start.o
endif
# LDFLAGS_vmlinux += -G 0 -static -n -nostdlib
# MODFLAGS += -mlong-calls
#
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
OBJCOPYFLAGS += -j .data.reloc -j .dtb.init.rodata
LDFLAGS_FINAL += --emit-relocs
endif
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_GO) += boot.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o udivdi3.o
# SPDX-License-Identifier: GPL-2.0+
-extra-$(CONFIG_SPL_BUILD) := start.o
+extra-$(CONFIG_XPL_BUILD) := start.o
obj-$(CONFIG_SOC_JZ4780) += jz4780/
void jz4780_tcu_wdt_start(void);
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
int jz_mmc_init(void __iomem *base);
#endif
#include <mmc.h>
#include <spl.h>
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* Pointer to the global data structure for SPL */
DECLARE_GLOBAL_DATA_PTR;
gd_t gdata __section(".bss");
hang();
}
-#endif /* CONFIG_SPL_BUILD */
+#endif /* CONFIG_XPL_BUILD */
phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
.globl _start
.text
_start:
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/* magic value ("MSPL") */
.word 0x4d53504c
.end enable_caches
#endif /* CONFIG_SOC_JZ4780 */
-#endif /* !CONFIG_SPL_BUILD */
+#endif /* !CONFIG_XPL_BUILD */
ifneq ($(CONFIG_SOC_MT7621),y)
obj-y += ddr_init.o
obj-y += ddr_cal.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
endif
obj-$(CONFIG_SOC_MT7620) += mt7620/
return 0;
}
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
static int last_stage_init(void)
{
void *src, *dst;
obj-y += dram.o
obj-y += serial.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += sysc.o
endif
obj-y += init.o
obj-y += serial.o
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
ifeq ($(CONFIG_TPL_BUILD),y)
obj-y += tpl/
else
obj-y += lowlevel_init.o
obj-y += init.o
obj-y += ddr.o
-obj-$(CONFIG_SPL_BUILD) += serial.o
+obj-$(CONFIG_XPL_BUILD) += serial.o
endif
# Only test once
-ifneq ($(CONFIG_SPL_BUILD),y)
+ifneq ($(CONFIG_XPL_BUILD),y)
archprepare: checkgcc4
# GCC 3.x is reported to have problems generating the type of relocation
MINIMAL=
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
#endif
#if defined(CONFIG_NAND_SPL) || \
- (defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL))
+ (defined(CONFIG_XPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL))
#define MINIMAL_SPL
#endif
-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
+#if !defined(CONFIG_XPL_BUILD) && !defined(CONFIG_NAND_SPL) && \
!defined(CONFIG_SYS_RAMBOOT)
#define CFG_SYS_FLASHBOOT
#endif
/* Initialise the E300 processor core */
/*------------------------------------------*/
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
+#if (defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_MPC83XX_WAIT_FOR_NAND)) || \
defined(CONFIG_NAND_SPL)
/* The FCM begins execution after only the first page
* is loaded. Wait for the rest before branching
MINIMAL=
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
obj-$(CONFIG_MP) += release.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_CMD_ERRATA) += cmd_errata.o
endif
invalidate_tlb(1);
#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
- !(CONFIG_IS_ENABLED(INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
+ !(CONFIG_IS_ENABLED(INIT_MINIMAL) && defined(CONFIG_XPL_BUILD)) && \
!defined(CONFIG_NAND_SPL)
disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
#endif
#define LAW_EN 0x80000000
#if defined(CONFIG_NAND_SPL) || \
- (defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL))
+ (defined(CONFIG_XPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL))
#define MINIMAL_SPL
#endif
END_GOT
#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD)
/* Maximal size of the image */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
#define MAX_IMAGE_SIZE (CONFIG_SPL_MAX_SIZE - (CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512))
#else
#define MAX_IMAGE_SIZE CONFIG_SYS_L2_SIZE
#endif
-#if defined(CONFIG_SPL_BUILD) && CONFIG_SPL_MAX_SIZE < CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512
+#if defined(CONFIG_XPL_BUILD) && CONFIG_SPL_MAX_SIZE < CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512
#error "CONFIG_SPL_MAX_SIZE is too small for CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA"
#endif
/*
* For Targets without CONFIG_SPL like P3, P5
* and for targets with CONFIG_SPL like T1, T2, T4, only for
- * u-boot-spl i.e. CONFIG_SPL_BUILD
+ * u-boot-spl i.e. CONFIG_XPL_BUILD
*/
#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_NXP_ESBC) && \
- (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
+ (!defined(CONFIG_SPL) || defined(CONFIG_XPL_BUILD))
/* create a temp mapping in AS = 1 for mapping CONFIG_VAL(SYS_MONITOR_BASE)
* to L3 Address configured by PBL for ISBC code
*/
mr r10,r5 /* Save copy of Destination Address */
GET_GOT
-#if !defined(CONFIG_SPL_SKIP_RELOCATE) || !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_SKIP_RELOCATE) || !defined(CONFIG_XPL_BUILD)
mr r3,r5 /* Destination Address */
lis r4,CONFIG_VAL(SYS_MONITOR_BASE)@h /* Source Address */
ori r4,r4,CONFIG_VAL(SYS_MONITOR_BASE)@l
}
#if !defined(CONFIG_NAND_SPL) && \
- (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
+ (!defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
phys_addr_t *rpn)
{
print_size(memsize > CFG_MAX_MEM_MAPPED ?
memsize - CFG_MAX_MEM_MAPPED + size : size,
" of DDR memory left unmapped in U-Boot\n");
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
puts(" ");
#endif
}
MINIMAL=
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES;
/* Allocate space for Primary PAACT Table */
-#if (defined(CONFIG_SPL_BUILD) && defined(CFG_SPL_PPAACT_ADDR))
+#if (defined(CONFIG_XPL_BUILD) && defined(CFG_SPL_PPAACT_ADDR))
ppaact = (void *)CFG_SPL_PPAACT_ADDR;
#else
ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size);
memset(ppaact, 0, ppaact_size);
/* Allocate space for Secondary PAACT Table */
-#if (defined(CONFIG_SPL_BUILD) && defined(CFG_SPL_SPAACT_ADDR))
+#if (defined(CONFIG_XPL_BUILD) && defined(CFG_SPL_SPAACT_ADDR))
sec = (void *)CFG_SPL_SPAACT_ADDR;
#else
sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size);
}
#if !defined(CONFIG_NAND_SPL) && \
- (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
+ (!defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
static int get_law_entry(u8 i, struct law_entry *e)
{
u32 lawar;
}
#if !defined(CONFIG_NAND_SPL) && \
- (!defined(CONFIG_SPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
+ (!defined(CONFIG_XPL_BUILD) || !CONFIG_IS_ENABLED(INIT_MINIMAL))
int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
u32 idx;
i++;
#endif
-#if (defined(CONFIG_SPL_BUILD) && (CFG_SYS_INIT_L3_VADDR))
+#if (defined(CONFIG_XPL_BUILD) && (CFG_SYS_INIT_L3_VADDR))
tbl->start_addr[i] =
(uint64_t)virt_to_phys((void *)CFG_SYS_INIT_L3_VADDR);
tbl->size[i] = 256 * 1024; /* 256K CPC flash */
#endif /* #ifdef CONFIG_NXP_ESBC */
#ifdef CONFIG_CHAIN_OF_TRUST
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
/*
* PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
* due to space crunch on CPC and thus malloc will not work.
#define CFG_SPL_SPAACT_ADDR 0x2f000000
#define CFG_SPL_JR0_LIODN_S 454
#define CFG_SPL_JR0_LIODN_NS 458
-#endif /* ifdef CONFIG_SPL_BUILD */
+#endif /* ifdef CONFIG_XPL_BUILD */
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
#include <config_fsl_chain_trust.h>
-#endif /* #ifndef CONFIG_SPL_BUILD */
+#endif /* #ifndef CONFIG_XPL_BUILD */
#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
#endif
MINIMAL=
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_INIT_MINIMAL
MINIMAL=y
obj-y += traps.o
endif # not minimal
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_$(SPL_TPL)_FRAMEWORK) += spl.o
endif
# Copyright (C) 2020 SiFive, Inc
# Pragnesh Patel <pragnesh.patel@sifive.com>
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
obj-y += spl.o
else
obj-y += dram.o
# Copyright (C) 2020-2021 SiFive, Inc
# Pragnesh Patel <pragnesh.patel@sifive.com>
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
obj-y += spl.o
else
obj-y += dram.o
#
# Copyright (C) 2022 StarFive Technology Co., Ltd.
-ifeq ($(CONFIG_SPL_BUILD),y)
+ifeq ($(CONFIG_XPL_BUILD),y)
obj-y += spl.o
else
obj-y += cpu.o
* Set stackpointer in internal/ex RAM to call board_init_f
*/
call_board_init_f:
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_STACK)
li t0, CONFIG_SPL_STACK
#else
li t0, SYS_INIT_SP_ADDR
la t5, board_init_f
jalr t5 /* jump to board_init_f() */
-#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_XPL_BUILD
spl_clear_bss:
la t0, __bss_start
la t1, __bss_end
j board_init_r
#endif
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD)
/*
* void relocate_code(addr_sp, gd, addr_moni)
*
* jump to it ...
*/
jr t4 /* jump to board_init_r() */
-#endif /* !defined(CONFIG_SPL_BUILD) */
+#endif /* !defined(CONFIG_XPL_BUILD) */
#if CONFIG_IS_ENABLED(SMP)
hart_out_of_bounds_loop:
endif
obj-y += setjmp.o
obj-$(CONFIG_$(SPL_)SMP) += smp.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
obj-y += fdt_fixup.o
obj-$(CONFIG_$(SPL)CMD_BDI) += bdinfo.o
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
void enable_caches(void)
{
struct udevice *dev;
probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev);
}
-#endif /* !CONFIG_SPL_BUILD */
+#endif /* !CONFIG_XPL_BUILD */
obj-y := cache.o cpu.o state.o
extra-y := start.o os.o
extra-$(CONFIG_SANDBOX_SDL) += sdl.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
obj-$(CONFIG_ETH_SANDBOX_RAW) += eth-raw-os.o
# os.c is build in the system environment, so needs standard includes
void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
-#if defined(CONFIG_PCI) && !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_PCI) && !defined(CONFIG_XPL_BUILD)
unsigned long plen = len;
void *ptr;
}
SANDBOX_CMDLINE_OPT_SHORT(help, 'h', 0, "Display help");
-#ifndef CONFIG_SPL_BUILD
+#ifndef CONFIG_XPL_BUILD
int sandbox_main_loop_init(void)
{
struct sandbox_state *state = state_get_current();
ifndef CONFIG_SPL
head-y := arch/x86/cpu/start.o
else
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
head-y = arch/x86/cpu/start_from_tpl.o
else
head-y = arch/x86/cpu/start_from_spl.o
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
IS_32BIT := y
else
ifndef CONFIG_X86_64
ifeq ($(IS_32BIT),y)
PLATFORM_CPPFLAGS += -march=i386 -m32
else
-PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -march=core2 -m64
+PLATFORM_CPPFLAGS += $(if $(CONFIG_XPL_BUILD),,-fpic) -fno-common -march=core2 -m64
ifndef CONFIG_X86_HARDFP
PLATFORM_CPPFLAGS += -mno-mmx -mno-sse
PLATFORM_CPPFLAGS += -mregparm=3
endif
KBUILD_LDFLAGS += --emit-relocs
-LDFLAGS_FINAL += --gc-sections $(if $(CONFIG_SPL_BUILD),,-pie)
+LDFLAGS_FINAL += --gc-sections $(if $(CONFIG_XPL_BUILD),,-pie)
endif
ifdef CONFIG_X86_64
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
PLATFORM_CPPFLAGS += -D__x86_64__
else
PLATFORM_CPPFLAGS += -D__I386__
ifndef CONFIG_SPL
extra-y = start.o
else
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
extra-y = start_from_tpl.o
else
extra-y = start_from_spl.o
#
# Copyright 2019 Google LLC
-obj-$(CONFIG_SPL_BUILD) += cpu_spl.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
-obj-$(CONFIG_SPL_BUILD) += systemagent.o
+obj-$(CONFIG_XPL_BUILD) += cpu_spl.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
+obj-$(CONFIG_XPL_BUILD) += systemagent.o
obj-y += cpu_common.o
ifndef CONFIG_TPL_BUILD
obj-y += cpu.o
obj-y += punit.o
obj-y += fsp_bindings.o
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += fsp_m.o
endif
endif
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += acpi.o
obj-y += fsp_s.o
endif
return 0;
}
-#if defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_XPL_BUILD)
const struct fsp_binding fsp_m_bindings[] = {
{
.type = FSP_UINT32,
}
#endif
-#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+#if !defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD)
const struct fsp_binding fsp_s_bindings[] = {
{
.type = FSP_UINT8,
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += cpu_full.o
ifdef CONFIG_SPL
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += cpu_from_spl.o
obj-y += cpu_full.o
obj-y += refcode.o
endif
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
# obj-y += cpu_from_spl.o
obj-y += adsp.o
obj-y += sata.o
[0x11] = 128,
};
-#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+#if defined(CONFIG_XPL_BUILD) && !defined(CONFIG_TPL_BUILD)
int arch_cpu_init(void)
{
return 0;
return broadwell_pch_early_init(dev);
else
return broadwell_pch_init(dev);
- } else if (IS_ENABLED(CONFIG_SPL) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
+ } else if (IS_ENABLED(CONFIG_SPL) && !IS_ENABLED(CONFIG_XPL_BUILD)) {
return broadwell_pch_init(dev);
} else {
return 0;
LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16)
ifdef CONFIG_X86_64
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_EFI_APP),)
+ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_EFI_APP),)
LDSCRIPT = $(srctree)/arch/x86/cpu/u-boot-64.lds
endif
endif
ifndef CONFIG_SPL
obj-y += car.o
endif
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
obj-y += coreboot_spl.o
else
obj-y += sdram.o
static int last_stage_init(void)
{
- if (IS_ENABLED(CONFIG_SPL_BUILD))
+ if (IS_ENABLED(CONFIG_XPL_BUILD))
return 0;
board_final_init();
#endif
#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB) && \
- !defined(CONFIG_SPL_BUILD)
+ !defined(CONFIG_XPL_BUILD)
/*
* Implement a weak default function for boards that need to do some final init
* before the system is ready.
}
EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
-#endif /* !SYS_COREBOOT && !EFI_STUB && !SPL_BUILD */
+#endif /* !SYS_COREBOOT && !EFI_STUB && !XPL_BUILD */
static int x86_init_cpus(void)
{
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
endif
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_INTEL_GMA_ACPI) += intel_opregion.o
endif
ifdef CONFIG_INTEL_CAR_CQOS
obj-$(CONFIG_TPL_BUILD) += car2.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += car2_uninit.o
endif
endif
obj-$(CONFIG_HAVE_P2SB) += p2sb.o
ifdef CONFIG_SPL
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
ifndef CONFIG_SYS_COREBOOT
obj-y += cpu_from_spl.o
endif
obj-y += early_me.o
obj-y += lpc.o
obj-y += northbridge.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-y += sata.o
endif
obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += sdram.o
* Our assembly routines do not work on in 64-bit mode and we don't do a lot of
* copying in SPL, so code size is more important there.
*/
-#if defined(CONFIG_SPL_BUILD) || !IS_ENABLED(CONFIG_X86_32BIT_INIT)
+#if defined(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_X86_32BIT_INIT)
#undef __HAVE_ARCH_MEMCPY
extern void *memcpy(void *, const void *, __kernel_size_t);
obj-y += bios_interrupts.o
endif
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_X86_32BIT_INIT) += string.o
endif
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_CMD_BOOTM) += bootm.o
endif
obj-y += cmd_boot.o
obj-$(CONFIG_$(SPL_TPL_)GENERATE_ACPI_TABLE) += acpi_table.o
endif
obj-y += tables.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_ZBOOT) += zimage.o
endif
obj-$(CONFIG_USE_HOB) += hob.o
obj-$(CONFIG_FSP_VERSION2) += fsp2/
endif
-ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_XPL_BUILD
ifdef CONFIG_TPL_BUILD
obj-y += tpl.o
else
else
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),)
extra-y += $(EFI_CRT0) $(EFI_RELOC)
endif
obj-y += fsp_common.o
obj-y += fsp_dram.o
-ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_XPL_BUILD
obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o
endif
obj-y += fsp_support.o
projects / u-boot.git / commitdiff
