source "board/hisilicon/hikey960/Kconfig"
source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
-source "board/silica/pengwyn/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
select DM_SERIAL
imply CMD_DM
-config TARGET_PENGWYN
- bool "Support pengwyn"
- select DM
- select DM_GPIO
- select DM_SERIAL
- imply CMD_DM
-
config TARGET_PHYCORE_AM335X_R2
bool "Support phyCORE AM335X R2"
select DM
+++ /dev/null
-if TARGET_PENGWYN
-
-config SYS_BOARD
- default "pengwyn"
-
-config SYS_VENDOR
- default "silica"
-
-config SYS_SOC
- default "am33xx"
-
-config SYS_CONFIG_NAME
- default "pengwyn"
-
-endif
+++ /dev/null
-PENGWYN BOARD
-M: Lothar Felten <lothar.felten@gmail.com>
-S: Maintained
-F: board/silica/pengwyn/
-F: include/configs/pengwyn.h
-F: configs/pengwyn_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Makefile
-#
-# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
-
-ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
-obj-y := mux.o
-endif
-
-obj-y += board.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * board.c
- *
- * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
- */
-
-#include <common.h>
-#include <env.h>
-#include <init.h>
-#include <net.h>
-#include <serial.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/ddr_defs.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sys_proto.h>
-#include <i2c.h>
-#include <phy.h>
-#include <cpsw.h>
-#include "board.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-#if defined(CONFIG_SPL_BUILD)
-
-/* DDR3 RAM timings */
-static const struct ddr_data ddr3_data = {
- .datardsratio0 = MT41K128MJT187E_RD_DQS,
- .datawdsratio0 = MT41K128MJT187E_WR_DQS,
- .datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
- .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
- .cmd0csratio = MT41K128MJT187E_RATIO,
- .cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
- .cmd1csratio = MT41K128MJT187E_RATIO,
- .cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
- .cmd2csratio = MT41K128MJT187E_RATIO,
- .cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
- .sdram_config = MT41K128MJT187E_EMIF_SDCFG,
- .ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
- .sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
- .sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
- .sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
- .zq_config = MT41K128MJT187E_ZQ_CFG,
- .emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
- PHY_EN_DYN_PWRDN,
-};
-
-const struct ctrl_ioregs ddr3_ioregs = {
- .cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
- .cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
- .cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE,
- .dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
- .dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
-};
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- return serial_tstc() && serial_getc() == 'c';
-}
-#endif
-
-#define OSC (V_OSCK/1000000)
-const struct dpll_params dpll_ddr_266 = {
- 266, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_303 = {
- 303, OSC-1, 1, -1, -1, -1, -1};
-const struct dpll_params dpll_ddr_400 = {
- 400, OSC-1, 1, -1, -1, -1, -1};
-
-void am33xx_spl_board_init(void)
-{
- /*
- * The pengwyn board uses the TPS650250 PMIC without I2C
- * interface and will output the following fixed voltages:
- * DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
- * VLDO1=1V8 (IO) VLDO2=1V8(IO)
- * Vcore=1V1 is fixed, generated by TPS62231
- */
-
- /* Get the frequency */
- dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
-
- /* Set CORE Frequencies to OPP100 */
- do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
-
- /* 720MHz cpu, this might change on newer board revisions */
- dpll_mpu_opp100.m = MPUPLL_M_720;
- do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
-}
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
- /* future configs can return other clock settings */
- return &dpll_ddr_303;
-}
-
-void set_uart_mux_conf(void)
-{
- enable_uart0_pin_mux();
-}
-
-void set_mux_conf_regs(void)
-{
- enable_board_pin_mux();
-}
-
-void sdram_init(void)
-{
- config_ddr(303, &ddr3_ioregs, &ddr3_data,
- &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
-#endif /* if CONFIG_SPL_BUILD */
-
-/*
- * Basic board specific setup. Pinmux has been handled already.
- */
-int board_init(void)
-{
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- gpmc_init();
- return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
- /* VTP can be added here */
- return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
- {
- .slave_reg_ofs = 0x208,
- .sliver_reg_ofs = 0xd80,
- .phy_addr = 1,
- .phy_if = PHY_INTERFACE_MODE_MII,
- },
-};
-
-static struct cpsw_platform_data cpsw_data = {
- .mdio_base = CPSW_MDIO_BASE,
- .cpsw_base = CPSW_BASE,
- .mdio_div = 0xff,
- .channels = 8,
- .cpdma_reg_ofs = 0x800,
- .slaves = 1,
- .slave_data = cpsw_slaves,
- .ale_reg_ofs = 0xd00,
- .ale_entries = 1024,
- .host_port_reg_ofs = 0x108,
- .hw_stats_reg_ofs = 0x900,
- .bd_ram_ofs = 0x2000,
- .mac_control = (1 << 5),
- .control = cpsw_control,
- .host_port_num = 0,
- .version = CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
- int rv, n = 0;
- uint8_t mac_addr[6];
- uint32_t mac_hi, mac_lo;
-
- if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
- printf("<ethaddr> not set. Reading from E-fuse\n");
- /* try reading mac address from efuse */
- mac_lo = readl(&cdev->macid0l);
- mac_hi = readl(&cdev->macid0h);
- mac_addr[0] = mac_hi & 0xFF;
- mac_addr[1] = (mac_hi & 0xFF00) >> 8;
- mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
- mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
- mac_addr[4] = mac_lo & 0xFF;
- mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
- if (is_valid_ethaddr(mac_addr))
- eth_env_set_enetaddr("ethaddr", mac_addr);
- else
- return n;
- }
-
- writel(MII_MODE_ENABLE, &cdev->miisel);
-
- rv = cpsw_register(&cpsw_data);
- if (rv < 0)
- printf("Error %d registering CPSW switch\n", rv);
- else
- n += rv;
- return n;
-}
-#endif /* if CONFIG_DRIVER_TI_CPSW */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * board.h
- *
- * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-void enable_uart0_pin_mux(void);
-void enable_board_pin_mux(void);
-
-#endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * mux.c
- *
- * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
- */
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/mux.h>
-#include <asm/io.h>
-#include "board.h"
-
-/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
-static struct module_pin_mux uart0_pin_mux[] = {
- {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
- {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
- {-1},
-};
-
-/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
-
-/* I2C pins C16(scl)/C17(sda) */
-static struct module_pin_mux i2c0_pin_mux[] = {
- {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */
- {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
- PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */
- {-1},
-};
-
-/* MMC0 pins */
-static struct module_pin_mux mmc0_pin_mux[] = {
- {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
- {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
- {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
- {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
- {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
- {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
- {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
- {-1},
-};
-
-/* MII pins */
-static struct module_pin_mux mii1_pin_mux[] = {
- {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
- {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
- {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
- {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
- {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
- {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
- {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
- {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
- {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
- {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
- {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
- {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
- {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
- {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
- {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
- {-1},
-};
-
-/* NAND pins */
-static struct module_pin_mux nand_pin_mux[] = {
- {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
- {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
- {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
- {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
- {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
- {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
- {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
- {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
- {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
- {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
- {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
- {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
- {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
- {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
- {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
- {-1},
-};
-
-void enable_uart0_pin_mux(void)
-{
- configure_module_pin_mux(uart0_pin_mux);
-}
-
-void enable_board_pin_mux()
-{
- configure_module_pin_mux(i2c0_pin_mux);
- configure_module_pin_mux(uart0_pin_mux);
- configure_module_pin_mux(mii1_pin_mux);
- configure_module_pin_mux(mmc0_pin_mux);
- configure_module_pin_mux(nand_pin_mux);
-}
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x4000
-CONFIG_AM33XX=y
-CONFIG_TARGET_PENGWYN=y
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_SPL_FS_FAT=y
-CONFIG_SPL_LIBDISK_SUPPORT=y
-CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_ETH_SUPPORT=y
-CONFIG_SPL_FS_EXT4=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_NET_SUPPORT=y
-CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_POWER_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SPL_YMODEM_SUPPORT=y
-CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x240000
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_EEPROM=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_BOOTP_DNS2=y
-CONFIG_CMD_WOL=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(SPL),512k(SPL.backup1),512k(SPL.backup2),512k(SPL.backup3),1536k(u-boot),512k(u-boot-spl-os),512k(u-boot-env),5m(kernel),-(rootfs)"
-CONFIG_CMD_DIAG=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_MII=y
-CONFIG_DRIVER_TI_CPSW=y
-CONFIG_SPI=y
-CONFIG_OMAP3_SPI=y
-CONFIG_USB=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_GADGET=y
-CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_GADGET=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * pengwyn.h
- *
- * Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
- *
- * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc.
- */
-
-#ifndef __CONFIG_PENGWYN_H
-#define __CONFIG_PENGWYN_H
-
-
-#include <configs/ti_am335x_common.h>
-
-/* Clock Defines */
-#define V_OSCK 24000000
-#define V_SCLK V_OSCK
-
-/* set env size */
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x80200000\0" \
- "fdtaddr=0x80F80000\0" \
- "bootpart=0:2\0" \
- "bootdir=/boot\0" \
- "bootfile=zImage\0" \
- "fdtfile=am335x-pengwyn.dtb\0" \
- "console=ttyO0,115200n8\0" \
- "optargs=\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 ro\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "rootpath=/export/rootfs\0" \
- "nfsopts=nolock\0" \
- "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
- "::off\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "netargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=/dev/nfs " \
- "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
- "ip=dhcp\0" \
- "bootenv=uEnv.txt\0" \
- "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
- "env import -t $loadaddr $filesize\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcloados=run mmcargs; " \
- "bootz ${loadaddr} - ${fdtaddr};\0" \
- "mmcboot=mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loadimage; then " \
- "run loadfdt;" \
- "run mmcloados;" \
- "fi;" \
- "fi;\0" \
- "netboot=echo Booting from network ...; " \
- "setenv autoload no; " \
- "dhcp; " \
- "tftp ${loadaddr} ${bootfile}; " \
- "tftp ${fdtaddr} ${fdtfile}; " \
- "run netargs; " \
- "bootz ${loadaddr} - ${fdtaddr}\0" \
- "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
- "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
- "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
- "nandrootfstype=ubifs rootwait=1\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${fdtaddr} u-boot-spl-os; " \
- "nand read ${loadaddr} kernel; " \
- "bootz ${loadaddr} - ${fdtaddr}\0"
-#endif
-
-#define CONFIG_BOOTCOMMAND \
- "run mmcboot;" \
- "run nandboot;"
-
-/* NS16550 Configuration: primary UART via FTDI */
-#define CONFIG_SYS_NS16550_COM1 0x44e09000
-
-/* I2C Configuration */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_ENV_EEPROM_IS_ON_I2C
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
-
-/* SPL */
-
-/* NAND support */
-
-/* NAND Configuration. */
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
- CONFIG_SYS_NAND_PAGE_SIZE)
-#define CONFIG_SYS_NAND_PAGE_SIZE 4096
-#define CONFIG_SYS_NAND_OOBSIZE 224
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128*4096)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
-#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
- 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
- 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,\
- 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,\
- 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,\
- 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\
- 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,\
- 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\
- 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153,\
- 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,\
- 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193,\
- 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209}
-
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 26
-#define CONFIG_SYS_NAND_ECCSTEPS 8
-#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
- CONFIG_SYS_NAND_ECCSTEPS)
-#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
-/* END NAND Configuration. */
-
-#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
-/* #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
-
-/* Size must be a multiple of Nand erase size (524288 b) */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
-/* NAND: SPL falcon mode configs */
-#ifdef CONFIG_SPL_OS_BOOT
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
-#endif
-
-/*
- * USB configuration. We enable MUSB support, both for host and for
- * gadget. We set USB0 as peripheral and USB1 as host, based on the
- * board schematic and physical port wired to each. Then for host we
- * add mass storage support.
- */
-#define CONFIG_AM335X_USB0
-#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
-#define CONFIG_AM335X_USB1
-#define CONFIG_AM335X_USB1_MODE MUSB_HOST
-
-/* Network */
-#define CONFIG_PHY_RESET 1
-
-#endif /* ! __CONFIG_PENGWYN_H */
projects / u-boot.git / commitdiff
