armv8: cache_v8: fix mmu_set_region_dcache_behaviour

The enum dcache_optoion contains a shift left 2 bits in the armv8 case
already.  The PMD_ATTRINDX(option) macro will perform a left shift of 2
bits.  Perform a right shift so that in the end we get the correct
value.

[trini: Reword the commit message]
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 7ebcaa21a169d7b07f76cdc1b89cce66480475e6..7c31d98a6f03157af1d72f28fe9c0162cdb7d02f 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -557,7 +557,7 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
                                     enum dcache_option option)
 {
-       u64 attrs = PMD_ATTRINDX(option);
+       u64 attrs = PMD_ATTRINDX(option >> 2);
        u64 real_start = start;
        u64 real_size = size;