armv8: fsl-lsch3: Initiaze 4 MACs per QSGMII in dpmac_info

Every QSGMII SerDes Protocol usage 4 MACs.

So add/repeat QSGMII information for 4 MACs in dpmac_info strucuture.

Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
index 02ca126ab80b85c90e7175f31f8d52ef8de0a032..ae0834365e4487ca01860a0bfbde7180367cecb9 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
@@ -90,7 +90,38 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
                else {
                        serdes_prtcl_map[lane_prtcl] = 1;
 #ifdef CONFIG_FSL_MC_ENET
-                       wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl);
+                       switch (lane_prtcl) {
+                       case QSGMII_A:
+                               wriop_init_dpmac(sd, 5, (int)lane_prtcl);
+                               wriop_init_dpmac(sd, 6, (int)lane_prtcl);
+                               wriop_init_dpmac(sd, 7, (int)lane_prtcl);
+                               wriop_init_dpmac(sd, 8, (int)lane_prtcl);
+                               break;
+                       case QSGMII_B:
+                               wriop_init_dpmac(sd, 1, (int)lane_prtcl);
+                               wriop_init_dpmac(sd, 2, (int)lane_prtcl);
+                               wriop_init_dpmac(sd, 3, (int)lane_prtcl);
+                               wriop_init_dpmac(sd, 4, (int)lane_prtcl);
+                               break;
+                       case QSGMII_C:
+                               wriop_init_dpmac(sd, 13, (int)lane_prtcl);
+                               wriop_init_dpmac(sd, 14, (int)lane_prtcl);
+                               wriop_init_dpmac(sd, 15, (int)lane_prtcl);
+                               wriop_init_dpmac(sd, 16, (int)lane_prtcl);
+                               break;
+                       case QSGMII_D:
+                               wriop_init_dpmac(sd, 9, (int)lane_prtcl);
+                               wriop_init_dpmac(sd, 10, (int)lane_prtcl);
+                               wriop_init_dpmac(sd, 11, (int)lane_prtcl);
+                               wriop_init_dpmac(sd, 12, (int)lane_prtcl);
+                               break;
+                       default:
+                                if (lane_prtcl >= SGMII1 &&
+                                          lane_prtcl <= SGMII16)
+                                       wriop_init_dpmac(sd, lane + 1,
+                                                        (int)lane_prtcl);
+                               break;
+                       }
 #endif
                }
        }