A number of different systems and vendors enable a vendor-specified
EEPROM that contains various identifying features.
+config SYS_EEPROM_BUS_NUM
+ int "I2C bus number of the system identifier EEPROM"
+ depends on ID_EEPROM
+ default 0
+
+choice
+ prompt "EEPROM starts with 'CCID' or 'NXID'"
+ depends on ID_EEPROM && (PPC || ARCH_LS1021A || FSL_LAYERSCAPE)
+ default SYS_I2C_EEPROM_NXID
+ help
+ Specify if the Freescale / NXP ID EEPROM starts with 'CCID' or 'NXID'
+ ASCII literal string.
+
+config SYS_I2C_EEPROM_CCID
+ bool "EEPROM starts with 'CCID'"
+
+config SYS_I2C_EEPROM_NXID
+ bool "EEPROM starts with 'NXID'"
+
+endchoice
+
config PCI_INIT_R
bool "Enumerate PCI buses during init"
depends on PCI
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
# CONFIG_MISC_INIT_R is not set
CONFIG_ID_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_CCID=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
# CONFIG_MISC_INIT_R is not set
CONFIG_ID_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_CCID=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
# CONFIG_MISC_INIT_R is not set
CONFIG_ID_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_CCID=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SPL_MAX_SIZE=0x1a000
CONFIG_SPL_PAD_TO=0x1c000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SPL_MAX_SIZE=0x1a000
CONFIG_SPL_PAD_TO=0x1c000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y
+CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SPL_MAX_SIZE=0x1a000
CONFIG_SPL_PAD_TO=0x1c000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
#endif
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_CCID
-
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
/* I2C EEPROM */
#if defined(CONFIG_TARGET_P1010RDB_PB)
-#ifdef CONFIG_ID_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#endif
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
#endif
/* enable read and write access to EEPROM */
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/*
* DDR Setup
*/
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/*
* DDR Setup
*/
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/*
* DDR Setup
*/
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/*
* DDR Setup
*/
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/*
* DDR Setup
*/
#define RTC
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR 0x40
* I2C
*/
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/*
* MMC
*/
/* GPIO */
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/*
* I2C bus multiplexer
*/
/* I2C */
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/* PCIe */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
/* GPIO */
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 1
-
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_SMP_PEN_ADDR 0x01ee0200
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
#define I2C_MUX_CH_DEFAULT 0x8
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/* DisplayPort */
#define DP_PWD_EN_DEFAULT_MASK 0x8
/* SATA */
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
#define CONFIG_SYS_SATA AHCI_BASE_ADDR
/*
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
-/* EEPROM */
-#ifndef SPL_NO_EEPROM
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-#endif
-
/*
* Environment
*/
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define I2C_RETIMER_ADDR 0x18
/* I2C bus multiplexer */
#define CFG_LPUART_EN 0x2
#endif
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/*
* IFC Definitions
*/
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define I2C_RETIMER_ADDR 0x18
/* PMIC */
#define RTC
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
#ifdef CONFIG_FSL_DSPI
#if !defined(CONFIG_TFABOOT) && \
!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#endif
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
#ifndef SPL_NO_ENV
/* Initial environment variables */
#ifdef CONFIG_TFABOOT
#define CONFIG_RTC_DS3231 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_NXP_ESBC
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#endif
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \
#define RTC
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/* Qixis */
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
/* MAC/PHY configuration */
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \
#define I2C_EMC2305_CMD 0x40
#define I2C_EMC2305_PWM 0x80
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \
/* RTC */
#define CONFIG_SYS_RTC_BUS_NUM 0
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV
-#define CONFIG_SYS_EEPROM_BUS_NUM 0
-
#endif /* __SIFIVE_UNMATCHED_H */