]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
rockchip: rk3568-nanopi-r5: Enable PCIe on NanoPi R5C and R5S
authorJonas Karlman <jonas@kwiboo.se>
Wed, 2 Aug 2023 19:59:33 +0000 (19:59 +0000)
committerKever Yang <kever.yang@rock-chips.com>
Sat, 7 Oct 2023 02:23:32 +0000 (10:23 +0800)
Enable missing PCIe Kconfig options now that PCIe bifurcation is fixed
to make use of the two on-board RTL8125B and the M.2 slot on NanoPi R5C
and NanoPi R5S.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi
arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi
configs/nanopi-r5c-rk3568_defconfig
configs/nanopi-r5s-rk3568_defconfig

index fe5bc6af47657b751e184b71326c5751ccf3e247..c0798e950bb5fc7459192e7a73e1691a026348f0 100644 (file)
@@ -1,3 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
 #include "rk3568-nanopi-r5s-u-boot.dtsi"
+
+&pcie3x2 {
+       /delete-property/ vpcie3v3-supply;
+};
index 094e5af6a757629cd8dcbfe45bc08618ea95259b..880f8ff91fcbe93fc7ea3a9c20c211e0f98d7c9f 100644 (file)
        };
 };
 
+&pcie3x1 {
+       /delete-property/ vpcie3v3-supply;
+};
+
 &sdhci {
        cap-mmc-highspeed;
        mmc-ddr-1_8v;
index badac5805ddb24d53702213df5f9399f803754fc..833cff0e457de0eb3c114f22bd0586bcb1a52ea3 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_COUNTER_FREQUENCY=24000000
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
@@ -17,6 +18,7 @@ CONFIG_SPL_STACK=0x400000
 CONFIG_DEBUG_UART_BASE=0xFE660000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -39,6 +41,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
@@ -62,6 +65,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_SPL_PINCTRL=y
index fdcb0c266d83f21e8e09f2e894463f77c04caf1a..c278ce083d9a4137d5ced7166139c6914e01adb8 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_COUNTER_FREQUENCY=24000000
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_TEXT_BASE=0x00a00000
@@ -17,6 +18,7 @@ CONFIG_SPL_STACK=0x400000
 CONFIG_DEBUG_UART_BASE=0xFE660000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
@@ -39,6 +41,7 @@ CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_PMIC=y
 CONFIG_CMD_REGULATOR=y
@@ -62,6 +65,9 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_ROCKCHIP=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
 CONFIG_SPL_PINCTRL=y