for (i = 0; i < dsp->num_mems; i++) {
/* C71 cores only have a L1P Cache, there are no L1P SRAMs */
if (((device_is_compatible(dev, "ti,j721e-c71-dsp")) ||
- (device_is_compatible(dev, "ti,j721s2-c71-dsp"))) &&
+ (device_is_compatible(dev, "ti,j721s2-c71-dsp")) ||
+ (device_is_compatible(dev, "ti,am62a-c7xv-dsp"))) &&
!strcmp(mem_names[i], "l1pram")) {
dsp->mem[i].bus_addr = FDT_ADDR_T_NONE;
dsp->mem[i].dev_addr = FDT_ADDR_T_NONE;
dsp->mem[i].size = 0;
continue;
}
-
+ if (device_is_compatible(dev, "ti,am62a-c7xv-dsp") &&
+ !strcmp(mem_names[i], "l1dram")) {
+ dsp->mem[i].bus_addr = FDT_ADDR_T_NONE;
+ dsp->mem[i].dev_addr = FDT_ADDR_T_NONE;
+ dsp->mem[i].cpu_addr = NULL;
+ dsp->mem[i].size = 0;
+ continue;
+ }
dsp->mem[i].bus_addr = dev_read_addr_size_name(dev, mem_names[i],
(fdt_addr_t *)&dsp->mem[i].size);
if (dsp->mem[i].bus_addr == FDT_ADDR_T_NONE) {
{ .compatible = "ti,j721e-c66-dsp", .data = (ulong)&c66_data, },
{ .compatible = "ti,j721e-c71-dsp", .data = (ulong)&c71_data, },
{ .compatible = "ti,j721s2-c71-dsp", .data = (ulong)&c71_data, },
+ { .compatible = "ti,am62a-c7xv-dsp", .data = (ulong)&c71_data, },
{}
};