arm64: zynqmp: Use assigned-clock-rates for setting up clock in SOM

With limited low level configuration done via psu-init only IPs connected
on SOM are initialized and configured. All IPs connected to carrier card
are not initialized. There is a need to do proper reset, pin configuration
and also clock setting.
The patch targets the last part which is setting up proper clock for USBs
and SDs.
Also setup proper bus width for SD cards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/d9f80b2551bd246c3d7ecb09b516806c8dc83ed9.1645629459.git.michal.simek@xilinx.com

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 86b99070c4a8fe0c181c8b87aa3d90c98c559c82..7b09d75151863619382c6c072b5a35d11be986f8 100644 (file)
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -215,10 +215,12 @@
 
 &sdhci0 {
        clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
+       assigned-clocks = <&zynqmp_clk SDIO0_REF>;
 };
 
 &sdhci1 {
        clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
+       assigned-clocks = <&zynqmp_clk SDIO1_REF>;
 };
 
 &spi0 {
@@ -255,10 +257,12 @@
 
 &usb0 {
        clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+       assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
 };
 
 &usb1 {
        clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
+       assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
 };
 
 &watchdog0 {

diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index 34fb592d4fa51d1658ae40e6d26d7264ecc62344..f58ad69be3110b595e1f90d8360b7702d5900fe4 100644 (file)
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -154,6 +154,8 @@
        no-1-8-v;
        disable-wp;
        xlnx,mio-bank = <1>;
+       assigned-clock-rates = <187498123>;
+       bus-width = <8>;
 };
 
 &gem3 { /* required by spec */

diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 35247b0bbd2e30cfb84d018151a9865659a9716c..7236e03a5a74f063a1bd2aa791a29fb0d27de3c2 100644 (file)
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -109,6 +109,7 @@
        pinctrl-0 = <&pinctrl_usb0_default>;
        phy-names = "usb3-phy";
        phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+       assigned-clock-rates = <250000000>, <20000000>;
 
        usb5744: usb-hub { /* u43 */
                status = "okay";
@@ -140,6 +141,8 @@
        clk-phase-sd-hs = <126>, <60>;
        clk-phase-uhs-sdr25 = <120>, <60>;
        clk-phase-uhs-ddr50 = <126>, <48>;
+       assigned-clock-rates = <187498123>;
+       bus-width = <8>;
 };
 
 &gem3 { /* required by spec */

diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 5f55df28f3314edadb9c6c4417a49ab2b2dc1535..e9baf4cb4148ef4e29cd2fcc69b9b9dbf46d40c9 100644 (file)
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -189,6 +189,7 @@
        disable-wp;
        bus-width = <8>;
        xlnx,mio-bank = <0>;
+       assigned-clock-rates = <187498123>;
 };
 
 &spi1 { /* MIO6, 9-11 */