ARM: DRA72x: Update EMIF data

DRA72 has 1GB connected to EMIF1 only. Updating the details.
And also enable WA for BUG0039 only if corresponding EMIF is present.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tom Rini <trini@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 429c4becf3469e7061abc08e6799f54d48c62ff5..71c0cc8f2e440e0fbc72a77ae19e197cabf634b1 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1384,8 +1384,10 @@ void sdram_init(void)
 
        if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
            (!in_sdram && !warm_reset())) {
-               do_bug0039_workaround(EMIF1_BASE);
-               do_bug0039_workaround(EMIF2_BASE);
+               if (emif1_enabled)
+                       do_bug0039_workaround(EMIF1_BASE);
+               if (emif2_enabled)
+                       do_bug0039_workaround(EMIF2_BASE);
        }
 
        debug("<<sdram_init()\n");

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 1a6798d8b9b1f8cc4a128ce44588675d9d6e8bba..4baca11d7a93d9ef0c85f3f3f32f6cc2ace246dc 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -619,6 +619,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
+       case DRA722_ES1_0:
                *regs = &ioregs_dra7xx_es1;
                break;
 

diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 16a91f911a0c84bedadfd2e8010f612618b60b00..e2ebab826232709a599d1d91e443f942ca7e660f 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -229,6 +229,17 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
        .is_ma_present  = 0x1
 };
 
+/*
+ * DRA722 EVM EMIF1 CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
+       .dmm_lisa_map_0 = 0x0,
+       .dmm_lisa_map_1 = 0x0,
+       .dmm_lisa_map_2 = 0x80600100,
+       .dmm_lisa_map_3 = 0xFF020100,
+       .is_ma_present  = 0x1
+};
+
 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 {
        switch (omap_revision()) {
@@ -255,6 +266,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
                        break;
                }
                break;
+       case DRA722_ES1_0:
        default:
                *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
        }
@@ -275,8 +287,11 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
-       default:
                *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
+               break;
+       case DRA722_ES1_0:
+       default:
+               *dmm_lisa_regs = &lisa_map_2G_x_2;
        }
 
 }
@@ -463,6 +478,7 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
+       case DRA722_ES1_0:
                if (emif_nr == 1) {
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
                        *size =
@@ -630,6 +646,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
+       case DRA722_ES1_0:
                bug_00339_regs_ptr = dra_bug_00339_regs;
                *iterations = sizeof(dra_bug_00339_regs)/
                             sizeof(dra_bug_00339_regs[0]);