Add e6500 L2 replacement policy selection

This is compile-time config.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index d5b17de7c678098076ed940215a6329fb7332c6b..4067f053757a66cf21e2868ffd0808d40593153f 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -337,7 +337,7 @@ int enable_cluster_l2(void)
                        while ((in_be32(&l2cache->l2csr0)
                                & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
                                        ;
-                       out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE);
+                       out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
                }
                i++;
        } while (!(cluster & TP_CLUSTER_EOC));

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 87168e202dd8af194f7276cb2f113ff5977431ba..e413e4ae99266e3503a9d0ed9b26ce0f99bb61e4 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -735,6 +735,7 @@ enable_l2_cluster_l2:
        and.    r1, r0, r4
        bne     1b
        lis     r4, (L2CSR0_L2E|L2CSR0_L2PE)@h
+       ori     r4, r4, (L2CSR0_L2REP_MODE)@l
        sync
        stw     r4, 0(r3)       /* enable L2 */
 delete_ccsr_l2_tlb:

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 5c0c438e603a35eaa0ffd627a4bc4bff1c1ecc45..1760aa14c3686046bca7f18f5d919490558e57ab 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -507,6 +507,15 @@
 #define   L2CSR0_L2IO          0x00100000      /* L2 Cache Instruction Only */
 #define   L2CSR0_L2DO          0x00010000      /* L2 Cache Data Only */
 #define   L2CSR0_L2REP         0x00003000      /* L2 Line Replacement Algo */
+
+/* e6500 */
+#define   L2CSR0_L2REP_SPLRUAGE        0x00000000      /* L2REP Streaming PLRU with Aging */
+#define   L2CSR0_L2REP_FIFO    0x00001000      /* L2REP FIFO */
+#define   L2CSR0_L2REP_SPLRU   0x00002000      /* L2REP Streaming PLRU */
+#define   L2CSR0_L2REP_PLRU    0x00003000      /* L2REP PLRU */
+
+#define   L2CSR0_L2REP_MODE    L2CSR0_L2REP_SPLRUAGE
+
 #define   L2CSR0_L2FL          0x00000800      /* L2 Cache Flush */
 #define   L2CSR0_L2LFC         0x00000400      /* L2 Cache Lock Flash Clear */
 #define   L2CSR0_L2LOA         0x00000080      /* L2 Cache Lock Overflow Allocate */