ppc4xx: Convert PPC4xx UIC defines from lower case to upper case

The latest PPC4xx register cleanup patch missed the UIC defines.
This patch now changes lower case UIC defines to upper case.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
index 0db619952eb4c3d39369d70765177a12d76b2da1..482561122ae57533488218cc6c1a1feccb06ddef 100644 (file)
--- a/board/amcc/acadia/acadia.c
+++ b/board/amcc/acadia/acadia.c
@@ -78,12 +78,12 @@ int board_early_init_f(void)
        mfsdr(SDR0_ULTRA1, reg);
        mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
 
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000010);
-       mtdcr(uicpr, 0xFE7FFFF0);       /* set int polarities */
-       mtdcr(uictr, 0x00000010);       /* set int trigger levels */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
+       mtdcr(UIC0CR, 0x00000010);
+       mtdcr(UIC0PR, 0xFE7FFFF0);      /* set int polarities */
+       mtdcr(UIC0TR, 0x00000010);      /* set int trigger levels */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 
        return 0;
 }

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 2ffd720d5c4f80d29b56f6e0ceed816435c6ac96..38186a5d37894a77008cc8ec22e012bb37961f45 100644 (file)
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -392,21 +392,21 @@ int board_early_init_f(void)
        /*--------------------------------------------------------------------
         * Setup the interrupt controller polarities, triggers, etc.
         *-------------------------------------------------------------------*/
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000009);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 
        /*--------------------------------------------------------------------
         * Setup the GPIO pins

diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c
index d0aebec2cd49e7ecc666009727d9a7eecc9c3973..49eadb9212e87e40c248ae02a631fb6820778afa 100644 (file)
--- a/board/amcc/bubinga/bubinga.c
+++ b/board/amcc/bubinga/bubinga.c
@@ -29,12 +29,12 @@ long int spd_sdram(void);
 
 int board_early_init_f(void)
 {
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000010);
-       mtdcr(uicpr, 0xFFFF7FF0);       /* set int polarities */
-       mtdcr(uictr, 0x00000010);       /* set int trigger levels */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
+       mtdcr(UIC0CR, 0x00000010);
+       mtdcr(UIC0PR, 0xFFFF7FF0);      /* set int polarities */
+       mtdcr(UIC0TR, 0x00000010);      /* set int trigger levels */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 
        /*
         * Configure CPC0_PCI to enable PerWE as output

diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 3a03f307310cc5de4f30e6b92dec40eb84e025c9..f359d2377af22d5bb53f7c42f931d781cb350954 100644 (file)
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -116,37 +116,37 @@ int board_early_init_f(void)
        /*
         * Setup the interrupt controller polarities, triggers, etc.
         */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-       mtdcr(uic2er, 0x00000000);      /* disable all */
-       mtdcr(uic2cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic3sr, 0xffffffff);      /* clear all */
-       mtdcr(uic3er, 0x00000000);      /* disable all */
-       mtdcr(uic3cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic3pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic3tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic3vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic3sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC2ER, 0x00000000);      /* disable all */
+       mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC3SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC3ER, 0x00000000);      /* disable all */
+       mtdcr(UIC3CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC3PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC3TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC3VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC3SR, 0xffffffff);      /* clear all */
 
 #if !defined(CONFIG_ARCHES)
        /* SDR Setting - enable NDFC */

diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index 2439b03a9f7fce2cc79172653662f26fdd141518..0543bad138a84661afe6e35642ebc3ba8cfa3567 100644 (file)
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -71,21 +71,21 @@ int board_early_init_f(void)
        /*--------------------------------------------------------------------
         * Setup the interrupt controller polarities, triggers, etc.
         *-------------------------------------------------------------------*/
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000009);      /* SMI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000009);      /* SMI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 
        return 0;
 }

diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 1a45056daa04fb620f9cc60824c4a799f1eba5e8..bcef707403d856ce15811ea452c7faf3499901f2 100644 (file)
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -183,42 +183,42 @@ int board_early_init_f (void)
         * Set critical interrupt values.  Set interrupt polarities.  Set interrupt
         * trigger levels.  Make bit 0 High  priority.  Clear all interrupts again.
         *------------------------------------------------------------------------*/
-       mtdcr (uic3sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic3er, 0x00000000);     /* disable all interrupts */
-       mtdcr (uic3cr, 0x00000000);     /* Set Critical / Non Critical interrupts: */
-       mtdcr (uic3pr, 0xffffffff);     /* Set Interrupt Polarities*/
-       mtdcr (uic3tr, 0x001fffff);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic3vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
-       mtdcr (uic3sr, 0x00000000);     /* clear all  interrupts*/
-       mtdcr (uic3sr, 0xffffffff);     /* clear all  interrupts*/
-
-
-       mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic2er, 0x00000000);     /* disable all interrupts*/
-       mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical interrupts*/
-       mtdcr (uic2pr, 0xebebebff);     /* Set Interrupt Polarities*/
-       mtdcr (uic2tr, 0x74747400);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
-       mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
-       mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
-
-       mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts*/
-       mtdcr (uic1er, 0x00000000);     /* disable all interrupts*/
-       mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical interrupts*/
-       mtdcr (uic1pr, 0xffffffff);     /* Set Interrupt Polarities */
-       mtdcr (uic1tr, 0x001f8040);     /* Set Interrupt Trigger Levels*/
-       mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
-       mtdcr (uic1sr, 0x00000000);     /* clear all interrupts*/
-       mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts*/
-
-       mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic0er, 0x00000000);     /* disable all interrupts excepted cascade    to be checked */
-       mtdcr (uic0cr, 0x00104001);     /* Set Critical / Non Critical interrupts*/
-       mtdcr (uic0pr, 0xffffffff);     /* Set Interrupt Polarities*/
-       mtdcr (uic0tr, 0x010f0004);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
-       mtdcr (uic0sr, 0x00000000);     /* clear all interrupts*/
-       mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts*/
+       mtdcr (UIC3SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC3ER, 0x00000000);     /* disable all interrupts */
+       mtdcr (UIC3CR, 0x00000000);     /* Set Critical / Non Critical interrupts: */
+       mtdcr (UIC3PR, 0xffffffff);     /* Set Interrupt Polarities*/
+       mtdcr (UIC3TR, 0x001fffff);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC3VR, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
+       mtdcr (UIC3SR, 0x00000000);     /* clear all  interrupts*/
+       mtdcr (UIC3SR, 0xffffffff);     /* clear all  interrupts*/
+
+
+       mtdcr (UIC2SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC2ER, 0x00000000);     /* disable all interrupts*/
+       mtdcr (UIC2CR, 0x00000000);     /* Set Critical / Non Critical interrupts*/
+       mtdcr (UIC2PR, 0xebebebff);     /* Set Interrupt Polarities*/
+       mtdcr (UIC2TR, 0x74747400);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC2VR, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
+       mtdcr (UIC2SR, 0x00000000);     /* clear all interrupts */
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all interrupts */
+
+       mtdcr (UIC1SR, 0xffffffff);     /* Clear all interrupts*/
+       mtdcr (UIC1ER, 0x00000000);     /* disable all interrupts*/
+       mtdcr (UIC1CR, 0x00000000);     /* Set Critical / Non Critical interrupts*/
+       mtdcr (UIC1PR, 0xffffffff);     /* Set Interrupt Polarities */
+       mtdcr (UIC1TR, 0x001f8040);     /* Set Interrupt Trigger Levels*/
+       mtdcr (UIC1VR, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
+       mtdcr (UIC1SR, 0x00000000);     /* clear all interrupts*/
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all interrupts*/
+
+       mtdcr (UIC0SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all interrupts excepted cascade    to be checked */
+       mtdcr (UIC0CR, 0x00104001);     /* Set Critical / Non Critical interrupts*/
+       mtdcr (UIC0PR, 0xffffffff);     /* Set Interrupt Polarities*/
+       mtdcr (UIC0TR, 0x010f0004);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC0VR, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
+       mtdcr (UIC0SR, 0x00000000);     /* clear all interrupts*/
+       mtdcr (UIC0SR, 0xffffffff);     /* clear all interrupts*/
 
        mfsdr(SDR0_MFR, mfr);
        mfr |= SDR0_MFR_FIXD;           /* Workaround for PCI/DMA */

diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index 7e84a61a96da1a3e7d00f3c7de73bc96c8cee3df..5ebe69272c49d243b682eb5c1e1dd007d5a4b013 100644 (file)
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -158,33 +158,33 @@ int board_early_init_f (void)
         | interrupts again.
         +-------------------------------------------------------------------*/
 
-       mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic2er, 0x00000000);     /* disable all interrupts */
-       mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical interrupts */
-       mtdcr (uic2pr, 0xf7ffffff);     /* Set Interrupt Polarities */
-       mtdcr (uic2tr, 0x01e1fff8);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
-       mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
-       mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
-
-       mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic1er, 0x00000000);     /* disable all interrupts */
-       mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical interrupts */
-       mtdcr (uic1pr, 0xfffac785);     /* Set Interrupt Polarities */
-       mtdcr (uic1tr, 0x001d0040);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
-       mtdcr (uic1sr, 0x00000000);     /* clear all interrupts */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts */
-
-       mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic0er, 0x0000000a);     /* Disable all interrupts */
+       mtdcr (UIC2SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC2ER, 0x00000000);     /* disable all interrupts */
+       mtdcr (UIC2CR, 0x00000000);     /* Set Critical / Non Critical interrupts */
+       mtdcr (UIC2PR, 0xf7ffffff);     /* Set Interrupt Polarities */
+       mtdcr (UIC2TR, 0x01e1fff8);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC2VR, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
+       mtdcr (UIC2SR, 0x00000000);     /* clear all interrupts */
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all interrupts */
+
+       mtdcr (UIC1SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC1ER, 0x00000000);     /* disable all interrupts */
+       mtdcr (UIC1CR, 0x00000000);     /* Set Critical / Non Critical interrupts */
+       mtdcr (UIC1PR, 0xfffac785);     /* Set Interrupt Polarities */
+       mtdcr (UIC1TR, 0x001d0040);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC1VR, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
+       mtdcr (UIC1SR, 0x00000000);     /* clear all interrupts */
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all interrupts */
+
+       mtdcr (UIC0SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC0ER, 0x0000000a);     /* Disable all interrupts */
                                        /* Except cascade UIC0 and UIC1 */
-       mtdcr (uic0cr, 0x00000000);     /* Set Critical / Non Critical interrupts */
-       mtdcr (uic0pr, 0xffbfefef);     /* Set Interrupt Polarities */
-       mtdcr (uic0tr, 0x00007000);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
-       mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
-       mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
+       mtdcr (UIC0CR, 0x00000000);     /* Set Critical / Non Critical interrupts */
+       mtdcr (UIC0PR, 0xffbfefef);     /* Set Interrupt Polarities */
+       mtdcr (UIC0TR, 0x00007000);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC0VR, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
+       mtdcr (UIC0SR, 0x00000000);     /* clear all interrupts */
+       mtdcr (UIC0SR, 0xffffffff);     /* clear all interrupts */
 
        /*
         * Note: Some cores are still in reset when the chip starts, so

diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 71ad89fa6c3e3c922ded62ba2920b45b78c0ebe2..5f76672fb522a04e77c34a6710ed98ef908d6271 100644 (file)
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -49,23 +49,23 @@ int board_early_init_f(void)
        mtebc( PB2AP,  0x03800000 );
        mtebc( PB2CR,  0xff838000 );    /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
 
-       mtdcr( uic1sr, 0xffffffff );    /* Clear all interrupts */
-       mtdcr( uic1er, 0x00000000 );    /* disable all interrupts */
-       mtdcr( uic1cr, 0x00000000 );    /* Set Critical / Non Critical interrupts */
-       mtdcr( uic1pr, 0x7fff83ff );    /* Set Interrupt Polarities */
-       mtdcr( uic1tr, 0x001f8000 );    /* Set Interrupt Trigger Levels */
-       mtdcr( uic1vr, 0x00000001 );    /* Set Vect base=0,INT31 Highest priority */
-       mtdcr( uic1sr, 0x00000000 );    /* clear all interrupts */
-       mtdcr( uic1sr, 0xffffffff );
-
-       mtdcr( uic0sr, 0xffffffff );    /* Clear all interrupts */
-       mtdcr( uic0er, 0x00000000 );    /* disable all interrupts excepted cascade */
-       mtdcr( uic0cr, 0x00000001 );    /* Set Critical / Non Critical interrupts */
-       mtdcr( uic0pr, 0xffffffff );    /* Set Interrupt Polarities */
-       mtdcr( uic0tr, 0x01000004 );    /* Set Interrupt Trigger Levels */
-       mtdcr( uic0vr, 0x00000001 );    /* Set Vect base=0,INT31 Highest priority */
-       mtdcr( uic0sr, 0x00000000 );    /* clear all interrupts */
-       mtdcr( uic0sr, 0xffffffff );
+       mtdcr( UIC1SR, 0xffffffff );    /* Clear all interrupts */
+       mtdcr( UIC1ER, 0x00000000 );    /* disable all interrupts */
+       mtdcr( UIC1CR, 0x00000000 );    /* Set Critical / Non Critical interrupts */
+       mtdcr( UIC1PR, 0x7fff83ff );    /* Set Interrupt Polarities */
+       mtdcr( UIC1TR, 0x001f8000 );    /* Set Interrupt Trigger Levels */
+       mtdcr( UIC1VR, 0x00000001 );    /* Set Vect base=0,INT31 Highest priority */
+       mtdcr( UIC1SR, 0x00000000 );    /* clear all interrupts */
+       mtdcr( UIC1SR, 0xffffffff );
+
+       mtdcr( UIC0SR, 0xffffffff );    /* Clear all interrupts */
+       mtdcr( UIC0ER, 0x00000000 );    /* disable all interrupts excepted cascade */
+       mtdcr( UIC0CR, 0x00000001 );    /* Set Critical / Non Critical interrupts */
+       mtdcr( UIC0PR, 0xffffffff );    /* Set Interrupt Polarities */
+       mtdcr( UIC0TR, 0x01000004 );    /* Set Interrupt Trigger Levels */
+       mtdcr( UIC0VR, 0x00000001 );    /* Set Vect base=0,INT31 Highest priority */
+       mtdcr( UIC0SR, 0x00000000 );    /* clear all interrupts */
+       mtdcr( UIC0SR, 0xffffffff );
 
        mfsdr(SDR0_MFR, mfr);
        mfr |= SDR0_MFR_FIXD;           /* Workaround for PCI/DMA */

diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
index 9fc0ec6667ef282a25e53d3b59c4e91e544abdfa..fb0e7b75eb9bad44dfbd5bc65b9cfedc4508e7bc 100644 (file)
--- a/board/amcc/makalu/makalu.c
+++ b/board/amcc/makalu/makalu.c
@@ -159,33 +159,33 @@ int board_early_init_f (void)
         | interrupts again.
         +-------------------------------------------------------------------*/
 
-       mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic2er, 0x00000000);     /* disable all interrupts */
-       mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical interrupts */
-       mtdcr (uic2pr, 0xf7ffffff);     /* Set Interrupt Polarities */
-       mtdcr (uic2tr, 0x01e1fff8);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
-       mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
-       mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
+       mtdcr (UIC2SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC2ER, 0x00000000);     /* disable all interrupts */
+       mtdcr (UIC2CR, 0x00000000);     /* Set Critical / Non Critical interrupts */
+       mtdcr (UIC2PR, 0xf7ffffff);     /* Set Interrupt Polarities */
+       mtdcr (UIC2TR, 0x01e1fff8);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC2VR, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
+       mtdcr (UIC2SR, 0x00000000);     /* clear all interrupts */
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all interrupts */
 
-       mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic1er, 0x00000000);     /* disable all interrupts */
-       mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical interrupts */
-       mtdcr (uic1pr, 0xfffac785);     /* Set Interrupt Polarities */
-       mtdcr (uic1tr, 0x001d0040);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
-       mtdcr (uic1sr, 0x00000000);     /* clear all interrupts */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts */
+       mtdcr (UIC1SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC1ER, 0x00000000);     /* disable all interrupts */
+       mtdcr (UIC1CR, 0x00000000);     /* Set Critical / Non Critical interrupts */
+       mtdcr (UIC1PR, 0xfffac785);     /* Set Interrupt Polarities */
+       mtdcr (UIC1TR, 0x001d0040);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC1VR, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
+       mtdcr (UIC1SR, 0x00000000);     /* clear all interrupts */
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all interrupts */
 
-       mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic0er, 0x0000000a);     /* Disable all interrupts */
+       mtdcr (UIC0SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC0ER, 0x0000000a);     /* Disable all interrupts */
                                        /* Except cascade UIC0 and UIC1 */
-       mtdcr (uic0cr, 0x00000000);     /* Set Critical / Non Critical interrupts */
-       mtdcr (uic0pr, 0xffbfefef);     /* Set Interrupt Polarities */
-       mtdcr (uic0tr, 0x00007000);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
-       mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
-       mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
+       mtdcr (UIC0CR, 0x00000000);     /* Set Critical / Non Critical interrupts */
+       mtdcr (UIC0PR, 0xffbfefef);     /* Set Interrupt Polarities */
+       mtdcr (UIC0TR, 0x00007000);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC0VR, 0x00000001);     /* Set Vect base=0,INT31 Highest priority */
+       mtdcr (UIC0SR, 0x00000000);     /* clear all interrupts */
+       mtdcr (UIC0SR, 0xffffffff);     /* clear all interrupts */
 
        /*
         * Note: Some cores are still in reset when the chip starts, so

diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index 5e32e8a7844b6d3abdc4459b7c631f3f5382c6ae..8513f43a8f1ad7c71ce7d0ecf5071a18ed7f25cb 100644 (file)
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -159,36 +159,36 @@ int board_early_init_f (void)
         * UIC2         UIC1
         * UIC3         UIC2
         */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all */
-       mtdcr (uic1er, 0x00000000);     /* disable all */
-       mtdcr (uic1cr, 0x00000009);     /* SMI & UIC1 crit are critical */
-       mtdcr (uic1pr, 0xfffffe13);     /* per ref-board manual */
-       mtdcr (uic1tr, 0x01c00008);     /* per ref-board manual */
-       mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic2sr, 0xffffffff);     /* clear all */
-       mtdcr (uic2er, 0x00000000);     /* disable all */
-       mtdcr (uic2cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic2pr, 0xffffe0ff);     /* per ref-board manual */
-       mtdcr (uic2tr, 0x00ffc000);     /* per ref-board manual */
-       mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic2sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic3sr, 0xffffffff);     /* clear all */
-       mtdcr (uic3er, 0x00000000);     /* disable all */
-       mtdcr (uic3cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic3pr, 0xffffffff);     /* per ref-board manual */
-       mtdcr (uic3tr, 0x00ff8c0f);     /* per ref-board manual */
-       mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic3sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic0sr, 0xfc000000); /* clear all */
-       mtdcr (uic0er, 0x00000000); /* disable all */
-       mtdcr (uic0cr, 0x00000000); /* all non-critical */
-       mtdcr (uic0pr, 0xfc000000); /* */
-       mtdcr (uic0tr, 0x00000000); /* */
-       mtdcr (uic0vr, 0x00000001); /* */
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC1ER, 0x00000000);     /* disable all */
+       mtdcr (UIC1CR, 0x00000009);     /* SMI & UIC1 crit are critical */
+       mtdcr (UIC1PR, 0xfffffe13);     /* per ref-board manual */
+       mtdcr (UIC1TR, 0x01c00008);     /* per ref-board manual */
+       mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC2ER, 0x00000000);     /* disable all */
+       mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC2PR, 0xffffe0ff);     /* per ref-board manual */
+       mtdcr (UIC2TR, 0x00ffc000);     /* per ref-board manual */
+       mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC3SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC3ER, 0x00000000);     /* disable all */
+       mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC3PR, 0xffffffff);     /* per ref-board manual */
+       mtdcr (UIC3TR, 0x00ff8c0f);     /* per ref-board manual */
+       mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC3SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC0SR, 0xfc000000); /* clear all */
+       mtdcr (UIC0ER, 0x00000000); /* disable all */
+       mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+       mtdcr (UIC0PR, 0xfc000000); /* */
+       mtdcr (UIC0TR, 0x00000000); /* */
+       mtdcr (UIC0VR, 0x00000001); /* */
        mfsdr (SDR0_MFR, mfr);
        mfr &= ~SDR0_MFR_ECS_MASK;
 /*     mtsdr(SDR0_MFR, mfr); */

diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c
index 49078ebee2fa4fd3b3db612adbfb32ee31ad26f0..bc8cb0c443afa9ca7ef2aa292903f969051553cb 100644 (file)
--- a/board/amcc/redwood/redwood.c
+++ b/board/amcc/redwood/redwood.c
@@ -416,41 +416,41 @@ static void early_init_UIC(void)
         * interrupt trigger levels.  Make bit 0 High  priority.  Clear all
         * interrupts again.
         */
-       mtdcr(uic3sr, 0xffffffff);      /* Clear all interrupts */
-       mtdcr(uic3er, 0x00000000);      /* disable all interrupts */
-       mtdcr(uic3cr, 0x00000000);      /* Set Critical / Non Critical
+       mtdcr(UIC3SR, 0xffffffff);      /* Clear all interrupts */
+       mtdcr(UIC3ER, 0x00000000);      /* disable all interrupts */
+       mtdcr(UIC3CR, 0x00000000);      /* Set Critical / Non Critical
                                         * interrupts */
-       mtdcr(uic3pr, 0xffffffff);      /* Set Interrupt Polarities */
-       mtdcr(uic3tr, 0x001fffff);      /* Set Interrupt Trigger Levels */
-       mtdcr(uic3vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic3sr, 0xffffffff);      /* clear all  interrupts */
-
-       mtdcr(uic2sr, 0xffffffff);      /* Clear all interrupts */
-       mtdcr(uic2er, 0x00000000);      /* disable all interrupts */
-       mtdcr(uic2cr, 0x00000000);      /* Set Critical / Non Critical
+       mtdcr(UIC3PR, 0xffffffff);      /* Set Interrupt Polarities */
+       mtdcr(UIC3TR, 0x001fffff);      /* Set Interrupt Trigger Levels */
+       mtdcr(UIC3VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC3SR, 0xffffffff);      /* clear all  interrupts */
+
+       mtdcr(UIC2SR, 0xffffffff);      /* Clear all interrupts */
+       mtdcr(UIC2ER, 0x00000000);      /* disable all interrupts */
+       mtdcr(UIC2CR, 0x00000000);      /* Set Critical / Non Critical
                                         * interrupts */
-       mtdcr(uic2pr, 0xebebebff);      /* Set Interrupt Polarities */
-       mtdcr(uic2tr, 0x74747400);      /* Set Interrupt Trigger Levels */
-       mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all interrupts */
-
-       mtdcr(uic1sr, 0xffffffff);      /* Clear all interrupts */
-       mtdcr(uic1er, 0x00000000);      /* disable all interrupts */
-       mtdcr(uic1cr, 0x00000000);      /* Set Critical / Non Critical
+       mtdcr(UIC2PR, 0xebebebff);      /* Set Interrupt Polarities */
+       mtdcr(UIC2TR, 0x74747400);      /* Set Interrupt Trigger Levels */
+       mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all interrupts */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* Clear all interrupts */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all interrupts */
+       mtdcr(UIC1CR, 0x00000000);      /* Set Critical / Non Critical
                                         * interrupts */
-       mtdcr(uic1pr, 0xffffffff);      /* Set Interrupt Polarities */
-       mtdcr(uic1tr, 0x001fc0ff);      /* Set Interrupt Trigger Levels */
-       mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all interrupts */
+       mtdcr(UIC1PR, 0xffffffff);      /* Set Interrupt Polarities */
+       mtdcr(UIC1TR, 0x001fc0ff);      /* Set Interrupt Trigger Levels */
+       mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all interrupts */
 
-       mtdcr(uic0sr, 0xffffffff);      /* Clear all interrupts */
-       mtdcr(uic0er, 0x00000000);      /* disable all interrupts excepted
+       mtdcr(UIC0SR, 0xffffffff);      /* Clear all interrupts */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all interrupts excepted
                                         * cascade to be checked */
-       mtdcr(uic0cr, 0x00104001);      /* Set Critical / Non Critical
+       mtdcr(UIC0CR, 0x00104001);      /* Set Critical / Non Critical
                                         * interrupts */
-       mtdcr(uic0pr, 0xffffffff);      /* Set Interrupt Polarities */
-       mtdcr(uic0tr, 0x000f003c);      /* Set Interrupt Trigger Levels */
-       mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all interrupts */
+       mtdcr(UIC0PR, 0xffffffff);      /* Set Interrupt Polarities */
+       mtdcr(UIC0TR, 0x000f003c);      /* Set Interrupt Trigger Levels */
+       mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all interrupts */
 
 }

diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 5913455ba1559e25aa88d32001889ecd147c0313..17f831c3f41f1999f5868c8ff81d9758abf2cc8a 100644 (file)
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -52,29 +52,29 @@ int board_early_init_f(void)
        /*
         * Setup the interrupt controller polarities, triggers, etc.
         */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-       mtdcr(uic2er, 0x00000000);      /* disable all */
-       mtdcr(uic2cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xfffff7ff);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC2ER, 0x00000000);      /* disable all */
+       mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 
        /* 50MHz tmrclk */
        out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);

diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c
index 4e5796ee8280efbb955e7afdd0af61e8b2088dee..be381d60ac20c387b37630e61b187703cdeeeee6 100644 (file)
--- a/board/amcc/taihu/taihu.c
+++ b/board/amcc/taihu/taihu.c
@@ -40,13 +40,13 @@ int board_early_init_f(void)
 {
        lcd_init();
 
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);
-       mtdcr(uicpr, 0xFFFF7F00);       /* set int polarities */
-       mtdcr(uictr, 0x00000000);       /* set int trigger levels */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);
+       mtdcr(UIC0PR, 0xFFFF7F00);      /* set int polarities */
+       mtdcr(UIC0TR, 0x00000000);      /* set int trigger levels */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest priority */
 
        mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);     /* memory bank 3 (CPLD_LCM) initialization */
        mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);

diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index 086778a6523b95a61f3ed907e39355d7fdbbce78..4a0573eb3804b5cc5eb4c909d0d37f995395f66a 100644 (file)
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -132,36 +132,36 @@ int board_early_init_f (void)
         * UIC2         UIC1
         * UIC3         UIC2
         */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all */
-       mtdcr (uic1er, 0x00000000);     /* disable all */
-       mtdcr (uic1cr, 0x00000009);     /* SMI & UIC1 crit are critical */
-       mtdcr (uic1pr, 0xfffffe13);     /* per ref-board manual */
-       mtdcr (uic1tr, 0x01c00008);     /* per ref-board manual */
-       mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic2sr, 0xffffffff);     /* clear all */
-       mtdcr (uic2er, 0x00000000);     /* disable all */
-       mtdcr (uic2cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic2pr, 0xffffe0ff);     /* per ref-board manual */
-       mtdcr (uic2tr, 0x00ffc000);     /* per ref-board manual */
-       mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic2sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic3sr, 0xffffffff);     /* clear all */
-       mtdcr (uic3er, 0x00000000);     /* disable all */
-       mtdcr (uic3cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic3pr, 0xffffffff);     /* per ref-board manual */
-       mtdcr (uic3tr, 0x00ff8c0f);     /* per ref-board manual */
-       mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic3sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic0sr, 0xfc000000);     /* clear all */
-       mtdcr (uic0er, 0x00000000);     /* disable all */
-       mtdcr (uic0cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic0pr, 0xfc000000);     /* */
-       mtdcr (uic0tr, 0x00000000);     /* */
-       mtdcr (uic0vr, 0x00000001);     /* */
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC1ER, 0x00000000);     /* disable all */
+       mtdcr (UIC1CR, 0x00000009);     /* SMI & UIC1 crit are critical */
+       mtdcr (UIC1PR, 0xfffffe13);     /* per ref-board manual */
+       mtdcr (UIC1TR, 0x01c00008);     /* per ref-board manual */
+       mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC2ER, 0x00000000);     /* disable all */
+       mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC2PR, 0xffffe0ff);     /* per ref-board manual */
+       mtdcr (UIC2TR, 0x00ffc000);     /* per ref-board manual */
+       mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC3SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC3ER, 0x00000000);     /* disable all */
+       mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC3PR, 0xffffffff);     /* per ref-board manual */
+       mtdcr (UIC3TR, 0x00ff8c0f);     /* per ref-board manual */
+       mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC3SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC0SR, 0xfc000000);     /* clear all */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all */
+       mtdcr (UIC0CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC0PR, 0xfc000000);     /* */
+       mtdcr (UIC0TR, 0x00000000);     /* */
+       mtdcr (UIC0VR, 0x00000001);     /* */
 
        /* Enable two GPIO 10~11 and TraceA signal */
        mfsdr(SDR0_PFC0,reg);

diff --git a/board/amcc/walnut/walnut.c b/board/amcc/walnut/walnut.c
index 28dcb66ebc4bd3693b2ed183a9f4a783f99cfaa4..4f299324cd751585f813233e4868543ab5158702 100644 (file)
--- a/board/amcc/walnut/walnut.c
+++ b/board/amcc/walnut/walnut.c
@@ -47,13 +47,13 @@ int board_early_init_f(void)
          |
          +-------------------------------------------------------------------------*/
 
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000020);       /* set all but FPGA SMI to be non-critical */
-       mtdcr(uicpr, 0xFFFFFFE0);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
+       mtdcr(UIC0CR, 0x00000020);      /* set all but FPGA SMI to be non-critical */
+       mtdcr(UIC0PR, 0xFFFFFFE0);      /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest priority */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 
        /* set UART1 control to select CTS/RTS */
 #define FPGA_BRDC       0xF0300004

diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 2a654fa895ba8989df09f47eea2640c20f83a57f..731d441526f0d006f155da71b1d75d608f9da583 100644 (file)
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -82,21 +82,21 @@ int board_early_init_f(void)
        /*--------------------------------------------------------------------
         * Setup the interrupt controller polarities, triggers, etc.
         *-------------------------------------------------------------------*/
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000009);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 
        /*--------------------------------------------------------------------
         * Setup other serial configuration

diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 245004cee87f89c17a68682e77bbe7d9005e9711..033bdd20fa7b825d2fe0c3783c2bc21000488976 100644 (file)
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -485,50 +485,50 @@ int board_early_init_f (void)
         | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
         | interrupts again.
         +-------------------------------------------------------------------*/
-       mtdcr (uic3sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic3er, 0x00000000);     /* disable all interrupts */
-       mtdcr (uic3cr, 0x00000000);     /* Set Critical / Non Critical
+       mtdcr (UIC3SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC3ER, 0x00000000);     /* disable all interrupts */
+       mtdcr (UIC3CR, 0x00000000);     /* Set Critical / Non Critical
                                         * interrupts */
-       mtdcr (uic3pr, 0xffffffff);     /* Set Interrupt Polarities */
-       mtdcr (uic3tr, 0x001fffff);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic3vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
+       mtdcr (UIC3PR, 0xffffffff);     /* Set Interrupt Polarities */
+       mtdcr (UIC3TR, 0x001fffff);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC3VR, 0x00000001);     /* Set Vect base=0,INT31 Highest
                                         * priority */
-       mtdcr (uic3sr, 0x00000000);     /* clear all  interrupts */
-       mtdcr (uic3sr, 0xffffffff);     /* clear all  interrupts */
+       mtdcr (UIC3SR, 0x00000000);     /* clear all  interrupts */
+       mtdcr (UIC3SR, 0xffffffff);     /* clear all  interrupts */
 
-       mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic2er, 0x00000000);     /* disable all interrupts */
-       mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical
+       mtdcr (UIC2SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC2ER, 0x00000000);     /* disable all interrupts */
+       mtdcr (UIC2CR, 0x00000000);     /* Set Critical / Non Critical
                                         * interrupts */
-       mtdcr (uic2pr, 0xebebebff);     /* Set Interrupt Polarities */
-       mtdcr (uic2tr, 0x74747400);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
+       mtdcr (UIC2PR, 0xebebebff);     /* Set Interrupt Polarities */
+       mtdcr (UIC2TR, 0x74747400);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC2VR, 0x00000001);     /* Set Vect base=0,INT31 Highest
                                         * priority */
-       mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
-       mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
+       mtdcr (UIC2SR, 0x00000000);     /* clear all interrupts */
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all interrupts */
 
-       mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic1er, 0x00000000);     /* disable all interrupts */
-       mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical
+       mtdcr (UIC1SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC1ER, 0x00000000);     /* disable all interrupts */
+       mtdcr (UIC1CR, 0x00000000);     /* Set Critical / Non Critical
                                         * interrupts */
-       mtdcr (uic1pr, 0xffffffff);     /* Set Interrupt Polarities */
-       mtdcr (uic1tr, 0x001f8040);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
+       mtdcr (UIC1PR, 0xffffffff);     /* Set Interrupt Polarities */
+       mtdcr (UIC1TR, 0x001f8040);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC1VR, 0x00000001);     /* Set Vect base=0,INT31 Highest
                                         * priority */
-       mtdcr (uic1sr, 0x00000000);     /* clear all interrupts */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts */
+       mtdcr (UIC1SR, 0x00000000);     /* clear all interrupts */
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all interrupts */
 
-       mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
-       mtdcr (uic0er, 0x00000000);     /* disable all interrupts excepted
+       mtdcr (UIC0SR, 0xffffffff);     /* Clear all interrupts */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all interrupts excepted
                                         * cascade to be checked */
-       mtdcr (uic0cr, 0x00104001);     /* Set Critical / Non Critical
+       mtdcr (UIC0CR, 0x00104001);     /* Set Critical / Non Critical
                                         * interrupts */
-       mtdcr (uic0pr, 0xffffffff);     /* Set Interrupt Polarities */
-       mtdcr (uic0tr, 0x010f0004);     /* Set Interrupt Trigger Levels */
-       mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
+       mtdcr (UIC0PR, 0xffffffff);     /* Set Interrupt Polarities */
+       mtdcr (UIC0TR, 0x010f0004);     /* Set Interrupt Trigger Levels */
+       mtdcr (UIC0VR, 0x00000001);     /* Set Vect base=0,INT31 Highest
                                         * priority */
-       mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
-       mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
+       mtdcr (UIC0SR, 0x00000000);     /* clear all interrupts */
+       mtdcr (UIC0SR, 0xffffffff);     /* clear all interrupts */
 
        mfsdr(SDR0_MFR, mfr);
        mfr |= SDR0_MFR_FIXD;           /* Workaround for PCI/DMA */

diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
index 5d1c4170dd104fff4e1a2a5f3ad052c250faa896..79130711d4614ca17fbc4a9ec291aad03c5d64e5 100644 (file)
--- a/board/cray/L1/L1.c
+++ b/board/cray/L1/L1.c
@@ -113,13 +113,13 @@ int board_early_init_f (void)
 {
        /* Running from ROM: global data is still READONLY */
        init_sdram ();
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000020);      /* set all but FPGA SMI to be non-critical */
-       mtdcr (uicpr, 0xFFFFFFE0);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000020);     /* set all but FPGA SMI to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFFE0);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
        return 0;
 }
 

diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
index cb24cd4ffebddc4b8d565b35d8763c518bd05528..740e3ac6f5e9b22741cceb2d5dcc87647a4d361e 100644 (file)
--- a/board/csb272/csb272.c
+++ b/board/csb272/csb272.c
@@ -87,13 +87,13 @@ int board_early_init_f(void)
    |
    +-------------------------------------------------------------------------*/
 
-       mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
-       mtdcr (uicer, 0x00000000);   /* disable all ints */
-       mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
-       mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
-       mtdcr (uictr, 0x10000000);   /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
 
        mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
 

diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c
index fa0fa193e82da718a39790b10d88afad4df7f716..0c7760a02f8c419b82d7959554f338188ec4dcf8 100644 (file)
--- a/board/csb472/csb472.c
+++ b/board/csb472/csb472.c
@@ -55,13 +55,13 @@ int board_early_init_f(void)
    |
    +-------------------------------------------------------------------------*/
 
-       mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
-       mtdcr (uicer, 0x00000000);   /* disable all ints */
-       mtdcr (uiccr, 0x00000000);   /* set all to be non-critical */
-       mtdcr (uicpr, 0xFFFFFF83);   /* set int polarities */
-       mtdcr (uictr, 0x10000000);   /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);  /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);   /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
 
        mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
 

diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c
index 56751e1599509549bdbb7e6ae6bb0a9313be64e0..06de6e0b1d7075870a46dd824c5d061523d4b7d9 100644 (file)
--- a/board/dave/PPChameleonEVB/PPChameleonEVB.c
+++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c
@@ -53,13 +53,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5)
         * IRQ 31 (EXT IRQ 6)
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

diff --git a/board/eric/eric.c b/board/eric/eric.c
index bc2a907f6b97d523f7ee79e18534992e2b701d52..cfcfa525a9d86698f1fee45a75063033d67facb9 100644 (file)
--- a/board/eric/eric.c
+++ b/board/eric/eric.c
@@ -62,13 +62,13 @@ int board_early_init_f (void)
    |
    +-------------------------------------------------------------------------*/
 
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000000);      /* set all SMI to be non-critical */
-       mtdcr (uicpr, 0xFFFFFF88);      /* set int polarities; IRQ3 to 1 */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels, UART0 is EDGE */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);     /* set all SMI to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFF88);     /* set int polarities; IRQ3 to 1 */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels, UART0 is EDGE */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 
        mtdcr (CPC0_CR0, 0x00002000);   /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
 

diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
index 46622a29fd42688219bcb239cb8da35ee74eb868..409a0540bf7749ccf039f479a66ef10ea5cfd99d 100644 (file)
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -155,13 +155,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0 */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF81);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0 */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks

diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c
index 9d1b6d26442a6b98bfd5cdfd53e793a38bbec31e..a632cb42d611ff8d9340ae2dbacd892386e70f9a 100644 (file)
--- a/board/esd/ar405/ar405.c
+++ b/board/esd/ar405/ar405.c
@@ -130,13 +130,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000000);      /* set all to be non-critical */
-       mtdcr (uicpr, 0xFFFFFF81);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFF81);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 
        out_be16((void *)0xf03000ec, 0x0fff); /* enable interrupts in fpga */
 

diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c
index 8da08facffc4ba2f54b9c7ef875b79eea32b8114..5f0e67cbb4cac4ff0d1f8c4af37eaeb111af5349 100644 (file)
--- a/board/esd/ash405/ash405.c
+++ b/board/esd/ash405/ash405.c
@@ -66,13 +66,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c
index 418d3e237edcee14762755adf27c1ac623f7670d..5a3f61de3c184d19ca0d117589db3b80b12c41f8 100644 (file)
--- a/board/esd/canbt/canbt.c
+++ b/board/esd/canbt/canbt.c
@@ -134,13 +134,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000000);      /* set all to be non-critical */
-       mtdcr (uicpr, 0xFFFFFF81);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFF81);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 
        return 0;
 }

diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index 7a92401893d9f101171df0b05b5dfdde4b075c3a..391fbf4c1bd0f67602580428abc03b23daaa6b55 100644 (file)
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -45,13 +45,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
index 00c7024a85287231c707b7693cfa7a3a028557dc..6d9814f163f3cff764500a06243f46b2012bff96 100644 (file)
--- a/board/esd/cpci2dp/cpci2dp.c
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -58,14 +58,14 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) unused
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
-
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF81);      /* set int polarities */
+
+       mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 
        return 0;
 }

diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index 4c9ed2fa585ecd85923d81c28f6e24f5fa0a4b82..c29c876d6170b07a0e544616ff3ef16f8901b597 100644 (file)
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -179,22 +179,22 @@ int board_early_init_f(void)
         * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical*/
 #if defined(CONFIG_CPCI405_6U)
        if (cpci405_version() == 3) {
-               mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
+               mtdcr(UIC0PR, 0xFFFFFF99);      /* set int polarities */
        } else {
-               mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+               mtdcr(UIC0PR, 0xFFFFFF81);      /* set int polarities */
        }
 #else
-       mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
+       mtdcr(UIC0PR, 0xFFFFFF81);      /* set int polarities */
 #endif
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,
+       mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,
                                         * INT0 highest priority */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 
        return 0;
 }

diff --git a/board/esd/cpciiser4/cpciiser4.c b/board/esd/cpciiser4/cpciiser4.c
index 6e97392c4b64d3828a07848d0a2b4a64e337d900..ee90e2c28a5a3b83eb4b241072fffafb155ebf36 100644 (file)
--- a/board/esd/cpciiser4/cpciiser4.c
+++ b/board/esd/cpciiser4/cpciiser4.c
@@ -129,14 +129,14 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000000);      /* set all to be non-critical */
-       /*  mtdcr(uicpr, 0xFFFFFF81);   /  set int polarities */
-       mtdcr (uicpr, 0xFFFFFF80);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
+       /*  mtdcr(UIC0PR, 0xFFFFFF81);   /  set int polarities */
+       mtdcr (UIC0PR, 0xFFFFFF80);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 
        return 0;
 }

diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c
index fc0d091bca9ecd1039f1c313fe00f7fb0a5a84ae..228a57057a930691caa22ff2be7abd0aec7cdecb 100644 (file)
--- a/board/esd/dp405/dp405.c
+++ b/board/esd/dp405/dp405.c
@@ -43,13 +43,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c
index 28a50c7b0e77286ece1810eda7e40d3b51c0ebce..f475d11072d25841bdfff769377ea58f1d275060 100644 (file)
--- a/board/esd/du405/du405.c
+++ b/board/esd/du405/du405.c
@@ -124,13 +124,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) unused; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000000);      /* set all to be non-critical */
-       mtdcr (uicpr, 0xFFFFFFB1);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFFB1);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 100 us

diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index 376de98354816832a1a8be78daba72a27d317bf2..056f455d687ba27a9aa34fe4470ffd999bc07f74 100644 (file)
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -87,37 +87,37 @@ int board_early_init_f(void)
        /*
         * Setup the interrupt controller polarities, triggers, etc.
         */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xfffff7ff);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
 
        /*
         * UIC1:
         *  bit30: ext. Irq 1: PLD : int 32+30
         */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xfffffffd);
-       mtdcr(uic1tr, 0x00000000);
-       mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xfffffffd);
+       mtdcr(UIC1TR, 0x00000000);
+       mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 
        /*
         * UIC2
         *  bit3: ext. Irq 2: DCF77 : int 64+3
         */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-       mtdcr(uic2er, 0x00000000);      /* disable all */
-       mtdcr(uic2cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC2ER, 0x00000000);      /* disable all */
+       mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 
        /* select Ethernet pins */
        mfsdr(SDR0_PFC1, sdr0_pfc1);

diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
index b72b716ddf272b1afa9525b49a1083493b4328f1..132531b39c53cdfdca3a00dccd2d95b6fcfa977d 100644 (file)
--- a/board/esd/hh405/hh405.c
+++ b/board/esd/hh405/hh405.c
@@ -363,13 +363,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c
index acb23dad1f560440594c308c1dd06ee2153a4207..2a2c4343c0d26b5080a0b414d50cd78559a43878 100644 (file)
--- a/board/esd/hub405/hub405.c
+++ b/board/esd/hub405/hub405.c
@@ -86,13 +86,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c
index 709bcdd98026ee87595ebea257cd07b55b113fc8..ab909e503046acad8263d172f9f494df959852e9 100644 (file)
--- a/board/esd/ocrtc/ocrtc.c
+++ b/board/esd/ocrtc/ocrtc.c
@@ -45,13 +45,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000000);      /* set all to be non-critical */
-       mtdcr (uicpr, 0xFFFFFF81);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFF81);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 
        /*
         * EBC Configuration Register: clear EBTC -> high-Z ebc signals between

diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
index 04bc569ead1cc03a9088a2a3b0fbb19833b74ab4..34a163240115f275c2fa2fa6664c8f1692e439f1 100644 (file)
--- a/board/esd/pci405/pci405.c
+++ b/board/esd/pci405/pci405.c
@@ -155,13 +155,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
-       mtdcr(uicer, 0x00000000);        /* disable all ints */
-       mtdcr(uiccr, 0x00000000);        /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF80);        /* set int polarities */
-       mtdcr(uictr, 0x10000000);        /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);       /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);        /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);        /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF80);        /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);        /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);       /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
 
        /*
         * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
@@ -271,7 +271,7 @@ int misc_init_r (void)
                                pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
                        }
                }
-               mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
+               mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
 
                *magic = 0;      /* clear pci reconfig magic again */
        }

diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
index a3c1cec6ef441d845d510550a7e8b476e5fd5350..f14ef7a20f843a88ff0f48e34ae22f2b11301a0e 100644 (file)
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@@ -78,13 +78,13 @@ int board_early_init_f(void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF99);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest prio */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF99);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest prio */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to

diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
index 5ff87e7a2503ce77f6d262a1f83777de9cc3bb02..e7415e44cb0bc7e368ed8861b39b286700587498 100644 (file)
--- a/board/esd/pmc405/pmc405.c
+++ b/board/esd/pmc405/pmc405.c
@@ -48,13 +48,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-       mtdcr(uicer, 0x00000000); /* disable all ints */
-       mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
-       mtdcr(uictr, 0x10000000); /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */
-       mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
+       mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
 
        /*
         * EBC Configuration Register:

diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c
index 419311aec83b5fa4a7516fb90b02e8f5d2efc6e8..3725ece3946cf90e85686220bb4c4adbd633ecc4 100644 (file)
--- a/board/esd/pmc405de/pmc405de.c
+++ b/board/esd/pmc405de/pmc405de.c
@@ -114,13 +114,13 @@ int board_early_init_f(void)
         * IRQ 30 (EXT IRQ 5) ETH1-PHY-IRQ#; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) PLD-IRQ#; active low; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0, INT0 highest prio */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0, INT0 highest prio */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register:

diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 119cbf2627312721b8b9a4ef098f72dffe30fa3a..f0f9bff3eb2d9f05b9e705f49394391720f977b2 100644 (file)
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -148,29 +148,29 @@ int board_early_init_f(void)
        /*
         * Setup the interrupt controller polarities, triggers, etc.
         */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xfffff7ef);
-       mtdcr(uic0tr, 0x00000000);
-       mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffc7f5);
-       mtdcr(uic1tr, 0x00000000);
-       mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-       mtdcr(uic2er, 0x00000000);      /* disable all */
-       mtdcr(uic2cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic2pr, 0x27ffffff);
-       mtdcr(uic2tr, 0x00000000);
-       mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xfffff7ef);
+       mtdcr(UIC0TR, 0x00000000);
+       mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffc7f5);
+       mtdcr(UIC1TR, 0x00000000);
+       mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC2ER, 0x00000000);      /* disable all */
+       mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC2PR, 0x27ffffff);
+       mtdcr(UIC2TR, 0x00000000);
+       mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 
        /* select Ethernet pins */
        mfsdr(SDR0_PFC1, sdr0_pfc1);

diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
index 7477f56b2b1ccb2bc01485941df05e3d7c0c8468..3f81665eb205b24a9e242cf56fbf290f14b69b72 100644 (file)
--- a/board/esd/voh405/voh405.c
+++ b/board/esd/voh405/voh405.c
@@ -88,13 +88,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFFB5);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFFB5);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c
index de9c7b974cfa85e0dc78361ea61398959ee9edf9..fb48022659946e81a6576393aabb6efc4f914818 100644 (file)
--- a/board/esd/vom405/vom405.c
+++ b/board/esd/vom405/vom405.c
@@ -45,13 +45,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c
index e86f1d0abc693de0a443905b9b6b3622b2676748..f2591d57f4f3245f6eaa6deca741060e20b2175d 100644 (file)
--- a/board/esd/wuh405/wuh405.c
+++ b/board/esd/wuh405/wuh405.c
@@ -64,13 +64,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF9F);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF9F);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c
index 0f8412776b6739b4b301a9a3d0676368f1d2ba46..ce6469d29e1c596889a658836406598e356bebba 100644 (file)
--- a/board/exbitgen/exbitgen.c
+++ b/board/exbitgen/exbitgen.c
@@ -37,13 +37,13 @@ int board_early_init_f (void)
    |
    +-------------------------------------------------------------------------*/
 
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000020);      /* set all but FPGA SMI to be non-critical */
-       mtdcr (uicpr, 0xFFFFFF90);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000020);     /* set all but FPGA SMI to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFF90);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 
        /* Perform reset of PHY connected to PPC via register in CPLD */
        out8 (PHY_CTRL_ADDR, 0x2e);     /* activate nRESET,FDX,F100,ANEN, enable output */

diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c
index ae258e1f2637d66f0421663561b4d7dd2d4272b1..8afffdc7372b6cbf1bd3845ea4b2cbbc1e78d158 100644 (file)
--- a/board/g2000/g2000.c
+++ b/board/g2000/g2000.c
@@ -38,20 +38,20 @@
 int board_early_init_f (void)
 {
 #if 0 /* test-only */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000010);
-       mtdcr (uicpr, 0xFFFF7FF0);      /* set int polarities */
-       mtdcr (uictr, 0x00000010);      /* set int trigger levels */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);      /* disable all ints */
+       mtdcr (UIC0CR, 0x00000010);
+       mtdcr (UIC0PR, 0xFFFF7FF0);      /* set int polarities */
+       mtdcr (UIC0TR, 0x00000010);      /* set int trigger levels */
+       mtdcr (UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 #else
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFFF0);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFFF0);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 #endif
 
 #if 1 /* test-only */

diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c
index 5246bc8c4fb88fd9983882d7c4a9455539f147b2..ff5f1832359f3cacbbd20630dad4adc864092ac9 100644 (file)
--- a/board/gdsys/dlvision/dlvision.c
+++ b/board/gdsys/dlvision/dlvision.c
@@ -36,13 +36,13 @@ enum {
 
 int board_early_init_f(void)
 {
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical */
-       mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest prio */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical */
+       mtdcr(UIC0PR, 0xFFFFFF80);      /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest prio */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks

diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
index 27c159bec62b25767ed6f2cab163ce7bfbca1c1d..7cc1bf26783d6432b6cbd73499b01b1ed4befe61 100644 (file)
--- a/board/gdsys/gdppc440etx/gdppc440etx.c
+++ b/board/gdsys/gdppc440etx/gdppc440etx.c
@@ -83,21 +83,21 @@ int board_early_init_f(void)
        /*
         * Setup the interrupt controller polarities, triggers, etc.
         */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000009);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 
        /*
         * Setup other serial configuration

diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
index 0de1be85792f6aa724b53eec2a1b7d96d2921ffe..2cd2e6d4503741504cf19ddee6db8715acd72194 100644 (file)
--- a/board/gdsys/intip/intip.c
+++ b/board/gdsys/intip/intip.c
@@ -44,37 +44,37 @@ int board_early_init_f(void)
        /*
         * Setup the interrupt controller polarities, triggers, etc.
         */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-       mtdcr(uic2er, 0x00000000);      /* disable all */
-       mtdcr(uic2cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic3sr, 0xffffffff);      /* clear all */
-       mtdcr(uic3er, 0x00000000);      /* disable all */
-       mtdcr(uic3cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic3pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic3tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic3vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic3sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC2ER, 0x00000000);      /* disable all */
+       mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC3SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC3ER, 0x00000000);      /* disable all */
+       mtdcr(UIC3CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC3PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC3TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC3VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC3SR, 0xffffffff);      /* clear all */
 
        /*
         * Configure PFC (Pin Function Control) registers

diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c
index 628ce3dc90b851258ebc5d730ee92edcdd862a1b..a56c2cc98794d688c0fa9fb2a7f40910c35ceed6 100644 (file)
--- a/board/gdsys/neo/neo.c
+++ b/board/gdsys/neo/neo.c
@@ -31,13 +31,13 @@
 
 int board_early_init_f(void)
 {
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical */
-       mtdcr(uicpr, 0xFFFFFF80);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest prio */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical */
+       mtdcr(UIC0PR, 0xFFFFFF80);      /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest prio */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks

diff --git a/board/jse/jse.c b/board/jse/jse.c
index 6dc9a01af8f3f2e968fee3ec44ebacccf08d87d7..1849ca47d77f01f902841ac7345c509429d7cc89 100644 (file)
--- a/board/jse/jse.c
+++ b/board/jse/jse.c
@@ -48,12 +48,12 @@ int board_early_init_f (void)
    |       IRQ 30 (EXT IRQ 5) SystemACE BRdy (unused)
    |       IRQ 31 (EXT IRQ 6) (unused)
    +-------------------------------------------------------------------------*/
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000000);      /* set all to be non-critical */
-       mtdcr (uicpr, 0xFFFFFF87);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFF87);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 
        /* Configure the interface to the SystemACE MCU port.
           The SystemACE is fast, but there is no reason to have

diff --git a/board/korat/korat.c b/board/korat/korat.c
index 3d4d149f6c64c0b879b583a50973d9a6e2be64ae..40a097cef59ef010d09857f49471f4db01535a54 100644 (file)
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -87,29 +87,29 @@ int board_early_init_f(void)
        /*
         * Setup the interrupt controller polarities, triggers, etc.
         */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-       mtdcr(uic2er, 0x00000000);      /* disable all */
-       mtdcr(uic2cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xfffff7ff);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC2ER, 0x00000000);      /* disable all */
+       mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
 
        /*
         * Take sim card reader and CF controller out of reset.  Also enable PHY

diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index a9c2a6f441a3549dad702e67e5c81033a99495d6..f4090f40dd3f1bf5a0d9d6584c43e9aba29cd00e 100644 (file)
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -44,29 +44,29 @@ int board_early_init_f(void)
        /*--------------------------------------------------------------------
         * Setup the interrupt controller polarities, triggers, etc.
         *-------------------------------------------------------------------*/
-       mtdcr(uic0sr, 0xffffffff);  /* clear all. if write with 1 then the status is cleared  */
-       mtdcr(uic0er, 0x00000000);  /* disable all */
-       mtdcr(uic0cr, 0x00000000);  /* we have not critical interrupts at the moment */
-       mtdcr(uic0pr, 0xFFBFF1EF);  /* Adjustment of the polarity */
-       mtdcr(uic0tr, 0x00000900);  /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-       mtdcr(uic0sr, 0xffffffff);  /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);  /* clear all */
-       mtdcr(uic1er, 0x00000000);  /* disable all */
-       mtdcr(uic1cr, 0x00000000);  /* all non-critical */
-       mtdcr(uic1pr, 0xFFFFC6A5);  /* Adjustment of the polarity */
-       mtdcr(uic1tr, 0x60000040);  /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-       mtdcr(uic1sr, 0xffffffff);  /* clear all */
-
-       mtdcr(uic2sr, 0xffffffff);  /* clear all */
-       mtdcr(uic2er, 0x00000000);  /* disable all */
-       mtdcr(uic2cr, 0x00000000);  /* all non-critical */
-       mtdcr(uic2pr, 0x27C00000);  /* Adjustment of the polarity */
-       mtdcr(uic2tr, 0x3C000000);  /* per ref-board manual */
-       mtdcr(uic2vr, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
-       mtdcr(uic2sr, 0xffffffff);  /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);  /* clear all. if write with 1 then the status is cleared  */
+       mtdcr(UIC0ER, 0x00000000);  /* disable all */
+       mtdcr(UIC0CR, 0x00000000);  /* we have not critical interrupts at the moment */
+       mtdcr(UIC0PR, 0xFFBFF1EF);  /* Adjustment of the polarity */
+       mtdcr(UIC0TR, 0x00000900);  /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
+       mtdcr(UIC0SR, 0xffffffff);  /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);  /* clear all */
+       mtdcr(UIC1ER, 0x00000000);  /* disable all */
+       mtdcr(UIC1CR, 0x00000000);  /* all non-critical */
+       mtdcr(UIC1PR, 0xFFFFC6A5);  /* Adjustment of the polarity */
+       mtdcr(UIC1TR, 0x60000040);  /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
+       mtdcr(UIC1SR, 0xffffffff);  /* clear all */
+
+       mtdcr(UIC2SR, 0xffffffff);  /* clear all */
+       mtdcr(UIC2ER, 0x00000000);  /* disable all */
+       mtdcr(UIC2CR, 0x00000000);  /* all non-critical */
+       mtdcr(UIC2PR, 0x27C00000);  /* Adjustment of the polarity */
+       mtdcr(UIC2TR, 0x3C000000);  /* per ref-board manual */
+       mtdcr(UIC2VR, 0x00000000);  /* int31 highest, base=0x000 is within DDRAM */
+       mtdcr(UIC2SR, 0xffffffff);  /* clear all */
 
        /* Trace Pins are disabled. SDR0_PFC0 Register */
        mtsdr(SDR0_PFC0, 0x0);

diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index d8279e81c988f2444f37b1215e5826cbcd2c6329..b87df01fec2648a4a65de7225254d6a421f66787 100644 (file)
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -489,13 +489,13 @@ int board_early_init_f (void)
    |       caused the interrupt.
    |
    +-------------------------------------------------------------------------*/
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000000);      /* set all to be non-critical (for now) */
-       mtdcr (uicpr, 0xFFFFFF80);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical (for now) */
+       mtdcr (UIC0PR, 0xFFFFFF80);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
        return 0;
 }
 

diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index e00d1d08f5cf59d9b6e7df64d9c1d8e853148c5e..c2d6c6fbcfacb9e811bfec2a97bac84992b1b293 100644 (file)
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -552,13 +552,13 @@ int board_early_init_f (void)
    |       caused the interrupt.
    |
    +-------------------------------------------------------------------------*/
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
-       mtdcr (uiccr, 0x00000000);      /* set all to be non-critical (for now) */
-       mtdcr (uicpr, 0xFFFFFF80);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical (for now) */
+       mtdcr (UIC0PR, 0xFFFFFF80);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 
        return 0;
 }

diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c
index 40bec8edcc5bfe9991370177d139dde74af99389..ba3e9c3cff1ef1adf6c9fd04146d99933ff381b1 100644 (file)
--- a/board/netstal/hcu4/hcu4.c
+++ b/board/netstal/hcu4/hcu4.c
@@ -58,12 +58,12 @@ int board_early_init_f (void)
         *      IRQ 17-24 RESERVED/UNUSED
         *      IRQ 31 (EXT IRQ 6) (unused)
         */
-       mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-       mtdcr(uicer, 0x00000000); /* disable all ints */
-       mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
-       mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
-       mtdcr(uictr, 0x00000000); /* set int trigger levels */
-       mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+       mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
+       mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+       mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
 
        mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
        mtdcr(CPC0_ECR, 0x60606000);

diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index 836c0346da30a98f1071f8f09e1474bcc6ad7858..4522612daef16ed4acf6e981c03a96d754cc6e45 100644 (file)
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -129,29 +129,29 @@ int board_early_init_f(void)
        /*
         * Setup the interrupt controller polarities, triggers, etc.
         */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000005);      /* ATI & UIC1 crit are critical */
-       mtdcr(uic0pr, 0xfffff7ff);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-       mtdcr(uic2er, 0x00000000);      /* disable all */
-       mtdcr(uic2cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic2pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic2tr, 0x00000000);      /* per ref-board manual */
-       mtdcr(uic2vr, 0x00000000);      /* int31 highest, base=0x000 */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
+       mtdcr(UIC0PR, 0xfffff7ff);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC2ER, 0x00000000);      /* disable all */
+       mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
+       mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
        mtsdr(SDR0_PFC0, 0x00003E00);   /* Pin function:  */
        mtsdr(SDR0_PFC1, 0x00848000);   /* Pin function: UART0 has 4 pins */
 

diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c
index 9054282c94d82568efaea7a3fd231d3f1f0f7de7..945d79aa200e9b91fef805c1b220e4643dd97feb 100644 (file)
--- a/board/netstal/mcu25/mcu25.c
+++ b/board/netstal/mcu25/mcu25.c
@@ -64,12 +64,12 @@ int board_early_init_f (void)
         *      IRQ 17-24 RESERVED/UNUSED
         *      IRQ 31 (EXT IRQ 6) (unused)
         */
-       mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
-       mtdcr(uicer, 0x00000000); /* disable all ints */
-       mtdcr(uiccr, 0x00000000); /* set all to be non-critical */
-       mtdcr(uicpr, 0xFFFFE000); /* set int polarities */
-       mtdcr(uictr, 0x00000000); /* set int trigger levels */
-       mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
+       mtdcr(UIC0PR, 0xFFFFE000); /* set int polarities */
+       mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
+       mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
 
        mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
        mtdcr(CPC0_ECR, 0x60606000);

diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index f966d02f1070db05362ef2e7edd22f22e99f0984..ac059a903b1946d7f6894f21dcad7a77384337b6 100644 (file)
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -155,21 +155,21 @@ int board_early_init_f(void)
        /*--------------------------------------------------------------------
         * Setup the interrupt controller polarities, triggers, etc.
         *-------------------------------------------------------------------*/
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000001);      /* UIC1 crit is critical */
-       mtdcr(uic0pr, 0xfffffe1f);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x01c00000);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000001);      /* UIC1 crit is critical */
+       mtdcr(UIC0PR, 0xfffffe1f);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x01c00000);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 
        /*--------------------------------------------------------------------
         * Setup other serial configuration

diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index be79b42bd041701309faf3be7a7f4f90099dcfe5..cdb91ac36b44d0c285ef2bfb9749ef31248a1c76 100644 (file)
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -60,36 +60,36 @@ int board_early_init_f (void)
         * UIC2         UIC1
         * UIC3         UIC2
         */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all */
-       mtdcr (uic1er, 0x00000000);     /* disable all */
-       mtdcr (uic1cr, 0x00000009);     /* SMI & UIC1 crit are critical */
-       mtdcr (uic1pr, 0xfffffe03);     /* per manual */
-       mtdcr (uic1tr, 0x01c00000);     /* per manual */
-       mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic2sr, 0xffffffff);     /* clear all */
-       mtdcr (uic2er, 0x00000000);     /* disable all */
-       mtdcr (uic2cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic2pr, 0xffffe0ff);     /* per ref-board manual */
-       mtdcr (uic2tr, 0x00ffc000);     /* per ref-board manual */
-       mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic2sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic3sr, 0xffffffff);     /* clear all */
-       mtdcr (uic3er, 0x00000000);     /* disable all */
-       mtdcr (uic3cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic3pr, 0xffffffff);     /* per ref-board manual */
-       mtdcr (uic3tr, 0x00ff8c0f);     /* per ref-board manual */
-       mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic3sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic0sr, 0xfc000000); /* clear all */
-       mtdcr (uic0er, 0x00000000); /* disable all */
-       mtdcr (uic0cr, 0x00000000); /* all non-critical */
-       mtdcr (uic0pr, 0xfc000000); /* */
-       mtdcr (uic0tr, 0x00000000); /* */
-       mtdcr (uic0vr, 0x00000001); /* */
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC1ER, 0x00000000);     /* disable all */
+       mtdcr (UIC1CR, 0x00000009);     /* SMI & UIC1 crit are critical */
+       mtdcr (UIC1PR, 0xfffffe03);     /* per manual */
+       mtdcr (UIC1TR, 0x01c00000);     /* per manual */
+       mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC2ER, 0x00000000);     /* disable all */
+       mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC2PR, 0xffffe0ff);     /* per ref-board manual */
+       mtdcr (UIC2TR, 0x00ffc000);     /* per ref-board manual */
+       mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC3SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC3ER, 0x00000000);     /* disable all */
+       mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC3PR, 0xffffffff);     /* per ref-board manual */
+       mtdcr (UIC3TR, 0x00ff8c0f);     /* per ref-board manual */
+       mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC3SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC0SR, 0xfc000000); /* clear all */
+       mtdcr (UIC0ER, 0x00000000); /* disable all */
+       mtdcr (UIC0CR, 0x00000000); /* all non-critical */
+       mtdcr (UIC0PR, 0xfc000000); /* */
+       mtdcr (UIC0TR, 0x00000000); /* */
+       mtdcr (UIC0VR, 0x00000001); /* */
 
        /* Setup shutdown/SSD empty interrupt as inputs */
        out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));

diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index 18054e45b6ee6bcbcce5e07623bdf7dfb534d816..20fd4dc2769cfa623c1b721dfcd08d0fc490ad76 100644 (file)
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -101,21 +101,21 @@ int board_early_init_f(void)
        /*--------------------------------------------------------------------
         * Setup the interrupt controller polarities, triggers, etc.
         *-------------------------------------------------------------------*/
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000001);      /* UIC1 crit is critical */
-       mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
-       mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
-       mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic0sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000001);      /* UIC1 crit is critical */
+       mtdcr(UIC0PR, 0xfffffe13);      /* per ref-board manual */
+       mtdcr(UIC0TR, 0x01c00008);      /* per ref-board manual */
+       mtdcr(UIC0VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC0SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC1PR, 0xffffe0ff);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x00ffc000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
 
        return 0;
 }

diff --git a/board/quad100hd/quad100hd.c b/board/quad100hd/quad100hd.c
index ffc47de25dccc3438ec45af14ecc08a25321d56a..f878c49bfad8bec9927356c888d63d72b1eec8ca 100644 (file)
--- a/board/quad100hd/quad100hd.c
+++ b/board/quad100hd/quad100hd.c
@@ -40,13 +40,13 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_early_init_f(void)
 {
        /* taken from PPCBoot */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);
-       mtdcr(uicpr, 0xFFFF7FFE);       /* set int polarities */
-       mtdcr(uictr, 0x00000000);       /* set int trigger levels */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);
+       mtdcr(UIC0PR, 0xFFFF7FFE);      /* set int polarities */
+       mtdcr(UIC0TR, 0x00000000);      /* set int trigger levels */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest priority */
 
        mtdcr(CPC0_SRR, 0x00040000);   /* Hold PCI bridge in reset */
 

diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
index b80c206940014cc44dfb9cb5ac5bed79c58fd604..92b15aa50fba70b3077a980a722e77f5e16d72db 100644 (file)
--- a/board/sandburst/karef/karef.c
+++ b/board/sandburst/karef/karef.c
@@ -212,36 +212,36 @@ int board_early_init_f (void)
         * UIC2         UIC1
         * UIC3         UIC2
         */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all */
-       mtdcr (uic1er, 0x00000000);     /* disable all */
-       mtdcr (uic1cr, 0x00000000);     /* all non- critical */
-       mtdcr (uic1pr, 0xfffffe03);     /* polarity */
-       mtdcr (uic1tr, 0x01c00000);     /* trigger edge vs level */
-       mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic2sr, 0xffffffff);     /* clear all */
-       mtdcr (uic2er, 0x00000000);     /* disable all */
-       mtdcr (uic2cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic2pr, 0xffffc8ff);     /* polarity */
-       mtdcr (uic2tr, 0x00ff0000);     /* trigger edge vs level */
-       mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic2sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic3sr, 0xffffffff);     /* clear all */
-       mtdcr (uic3er, 0x00000000);     /* disable all */
-       mtdcr (uic3cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic3pr, 0xffff83ff);     /* polarity */
-       mtdcr (uic3tr, 0x00ff8c0f);     /* trigger edge vs level */
-       mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic3sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic0sr, 0xfc000000);     /* clear all */
-       mtdcr (uic0er, 0x00000000);     /* disable all */
-       mtdcr (uic0cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic0pr, 0xfc000000);
-       mtdcr (uic0tr, 0x00000000);
-       mtdcr (uic0vr, 0x00000001);
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC1ER, 0x00000000);     /* disable all */
+       mtdcr (UIC1CR, 0x00000000);     /* all non- critical */
+       mtdcr (UIC1PR, 0xfffffe03);     /* polarity */
+       mtdcr (UIC1TR, 0x01c00000);     /* trigger edge vs level */
+       mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC2ER, 0x00000000);     /* disable all */
+       mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC2PR, 0xffffc8ff);     /* polarity */
+       mtdcr (UIC2TR, 0x00ff0000);     /* trigger edge vs level */
+       mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC3SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC3ER, 0x00000000);     /* disable all */
+       mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC3PR, 0xffff83ff);     /* polarity */
+       mtdcr (UIC3TR, 0x00ff8c0f);     /* trigger edge vs level */
+       mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC3SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC0SR, 0xfc000000);     /* clear all */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all */
+       mtdcr (UIC0CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC0PR, 0xfc000000);
+       mtdcr (UIC0TR, 0x00000000);
+       mtdcr (UIC0VR, 0x00000001);
 
        fpga_init();
 

diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
index ad3f9bc28e1f964443dc1b9068986a432a27f419..0c8e6dfb1ecbca94614cf7f311cb04efe7f69c05 100644 (file)
--- a/board/sandburst/metrobox/metrobox.c
+++ b/board/sandburst/metrobox/metrobox.c
@@ -202,36 +202,36 @@ int board_early_init_f (void)
         * UIC2         UIC1
         * UIC3         UIC2
         */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all */
-       mtdcr (uic1er, 0x00000000);     /* disable all */
-       mtdcr (uic1cr, 0x00000000);     /* all non- critical */
-       mtdcr (uic1pr, 0xfffffe03);     /* polarity */
-       mtdcr (uic1tr, 0x01c00000);     /* trigger edge vs level */
-       mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic1sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic2sr, 0xffffffff);     /* clear all */
-       mtdcr (uic2er, 0x00000000);     /* disable all */
-       mtdcr (uic2cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic2pr, 0xffffc8ff);     /* polarity */
-       mtdcr (uic2tr, 0x00ff0000);     /* trigger edge vs level */
-       mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic2sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic3sr, 0xffffffff);     /* clear all */
-       mtdcr (uic3er, 0x00000000);     /* disable all */
-       mtdcr (uic3cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic3pr, 0xffff83ff);     /* polarity */
-       mtdcr (uic3tr, 0x00ff8c0f);     /* trigger edge vs level */
-       mtdcr (uic3vr, 0x00000001);     /* int31 highest, base=0x000 */
-       mtdcr (uic3sr, 0xffffffff);     /* clear all */
-
-       mtdcr (uic0sr, 0xfc000000);     /* clear all */
-       mtdcr (uic0er, 0x00000000);     /* disable all */
-       mtdcr (uic0cr, 0x00000000);     /* all non-critical */
-       mtdcr (uic0pr, 0xfc000000);
-       mtdcr (uic0tr, 0x00000000);
-       mtdcr (uic0vr, 0x00000001);
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC1ER, 0x00000000);     /* disable all */
+       mtdcr (UIC1CR, 0x00000000);     /* all non- critical */
+       mtdcr (UIC1PR, 0xfffffe03);     /* polarity */
+       mtdcr (UIC1TR, 0x01c00000);     /* trigger edge vs level */
+       mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC1SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC2ER, 0x00000000);     /* disable all */
+       mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC2PR, 0xffffc8ff);     /* polarity */
+       mtdcr (UIC2TR, 0x00ff0000);     /* trigger edge vs level */
+       mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC2SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC3SR, 0xffffffff);     /* clear all */
+       mtdcr (UIC3ER, 0x00000000);     /* disable all */
+       mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC3PR, 0xffff83ff);     /* polarity */
+       mtdcr (UIC3TR, 0x00ff8c0f);     /* trigger edge vs level */
+       mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
+       mtdcr (UIC3SR, 0xffffffff);     /* clear all */
+
+       mtdcr (UIC0SR, 0xfc000000);     /* clear all */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all */
+       mtdcr (UIC0CR, 0x00000000);     /* all non-critical */
+       mtdcr (UIC0PR, 0xfc000000);
+       mtdcr (UIC0TR, 0x00000000);
+       mtdcr (UIC0VR, 0x00000001);
 
        fpga_init();
 

diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c
index 66842eaf4da8070eb8f9765b515f843c5e340e8b..74e6204db9e94eb51daed075bba639c40334243d 100644 (file)
--- a/board/sbc405/sbc405.c
+++ b/board/sbc405/sbc405.c
@@ -41,13 +41,13 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
-       mtdcr(uictr, 0x10000000);       /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF81);       /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us

diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c
index 5ae7b1244a7b61a0352f40573a6085d763c645fd..e7772c5ff6daa99740292d24d90a33cb24fd460e 100644 (file)
--- a/board/sc3/sc3.c
+++ b/board/sc3/sc3.c
@@ -294,22 +294,22 @@ int board_early_init_f (void)
 
        writeb (cpldConfig_1, CPLD_CONTROL_1);  /* disable everything in CPLD */
 
-       mtdcr (uicsr, 0xFFFFFFFF);    /* clear all ints */
-       mtdcr (uicer, 0x00000000);    /* disable all ints */
-       mtdcr (uiccr, 0x00000000);    /* set all to be non-critical */
+       mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);    /* disable all ints */
+       mtdcr (UIC0CR, 0x00000000);    /* set all to be non-critical */
 
        if (IS_CAMERON) {
                sc3_cameron_init();
                mtdcr (0x0B6, 0x18000000);
-               mtdcr (uicpr, 0xFFFFFFF0);
-               mtdcr (uictr, 0x10001030);
+               mtdcr (UIC0PR, 0xFFFFFFF0);
+               mtdcr (UIC0TR, 0x10001030);
        } else {
                mtdcr (0x0B6, 0x0000000);
-               mtdcr (uicpr, 0xFFFFFFE0);
-               mtdcr (uictr, 0x10000020);
+               mtdcr (UIC0PR, 0xFFFFFFE0);
+               mtdcr (UIC0TR, 0x10000020);
        }
-       mtdcr (uicvcr, 0x00000001);   /* set vect base=0,INT0 highest priority */
-       mtdcr (uicsr, 0xFFFFFFFF);    /* clear all ints */
+       mtdcr (UIC0VCR, 0x00000001);   /* set vect base=0,INT0 highest priority */
+       mtdcr (UIC0SR, 0xFFFFFFFF);    /* clear all ints */
 
        /* setup other implementation specific details */
        mtdcr (CPC0_ECR, 0x60606000);

diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c
index 6479beeb13bb612cc7cd1f1384ff0e6a55327610..00a9f98b44c8a34f9b74773cfee00ec5c15268f6 100644 (file)
--- a/board/w7o/w7o.c
+++ b/board/w7o/w7o.c
@@ -64,16 +64,16 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive
         */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
 
-       mtdcr (uiccr, 0x00000000);      /* set all to be non-critical */
-       mtdcr (uicpr, 0xFFFFFF80);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,
+       mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFF80);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,
                                           INT0 highest priority */
 
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 
 #elif defined(CONFIG_W7OLMC)
        /*
@@ -95,16 +95,16 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive
         */
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
-       mtdcr (uicer, 0x00000000);      /* disable all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
+       mtdcr (UIC0ER, 0x00000000);     /* disable all ints */
 
-       mtdcr (uiccr, 0x00000000);      /* set all to be non-critical */
-       mtdcr (uicpr, 0xFFFFFF80);      /* set int polarities */
-       mtdcr (uictr, 0x10000000);      /* set int trigger levels */
-       mtdcr (uicvcr, 0x00000001);     /* set vect base=0,
+       mtdcr (UIC0CR, 0x00000000);     /* set all to be non-critical */
+       mtdcr (UIC0PR, 0xFFFFFF80);     /* set int polarities */
+       mtdcr (UIC0TR, 0x10000000);     /* set int trigger levels */
+       mtdcr (UIC0VCR, 0x00000001);    /* set vect base=0,
                                           INT0 highest priority */
 
-       mtdcr (uicsr, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr (UIC0SR, 0xFFFFFFFF);     /* clear all ints */
 
 #else  /* Unknown */
 #    error "Unknown W7O board configuration"

diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c
index 58041fcd3498cabcd4bf6e6a9c1933f0f278d4f6..011fb94bb63234d147a507de669097c91b0bee7e 100644 (file)
--- a/board/xes/xpedite1000/xpedite1000.c
+++ b/board/xes/xpedite1000/xpedite1000.c
@@ -74,36 +74,36 @@ int board_early_init_f(void)
         * UIC2         UIC1
         * UIC3         UIC2
         */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-       mtdcr(uic1er, 0x00000000);      /* disable all */
-       mtdcr(uic1cr, 0x00000003);      /* SMI & UIC1 crit are critical */
-       mtdcr(uic1pr, 0xfffffe00);      /* per ref-board manual */
-       mtdcr(uic1tr, 0x01c00000);      /* per ref-board manual */
-       mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic1sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-       mtdcr(uic2er, 0x00000000);      /* disable all */
-       mtdcr(uic2cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic2pr, 0xffffc0ff);      /* per ref-board manual */
-       mtdcr(uic2tr, 0x00ff8000);      /* per ref-board manual */
-       mtdcr(uic2vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic2sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic3sr, 0xffffffff);      /* clear all */
-       mtdcr(uic3er, 0x00000000);      /* disable all */
-       mtdcr(uic3cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic3pr, 0xffffffff);      /* per ref-board manual */
-       mtdcr(uic3tr, 0x00ff8c0f);      /* per ref-board manual */
-       mtdcr(uic3vr, 0x00000001);      /* int31 highest, base=0x000 */
-       mtdcr(uic3sr, 0xffffffff);      /* clear all */
-
-       mtdcr(uic0sr, 0xfc000000);      /* clear all */
-       mtdcr(uic0er, 0x00000000);      /* disable all */
-       mtdcr(uic0cr, 0x00000000);      /* all non-critical */
-       mtdcr(uic0pr, 0xfc000000);      /* */
-       mtdcr(uic0tr, 0x00000000);      /* */
-       mtdcr(uic0vr, 0x00000001);      /* */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC1ER, 0x00000000);      /* disable all */
+       mtdcr(UIC1CR, 0x00000003);      /* SMI & UIC1 crit are critical */
+       mtdcr(UIC1PR, 0xfffffe00);      /* per ref-board manual */
+       mtdcr(UIC1TR, 0x01c00000);      /* per ref-board manual */
+       mtdcr(UIC1VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC1SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC2ER, 0x00000000);      /* disable all */
+       mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC2PR, 0xffffc0ff);      /* per ref-board manual */
+       mtdcr(UIC2TR, 0x00ff8000);      /* per ref-board manual */
+       mtdcr(UIC2VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC2SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC3SR, 0xffffffff);      /* clear all */
+       mtdcr(UIC3ER, 0x00000000);      /* disable all */
+       mtdcr(UIC3CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC3PR, 0xffffffff);      /* per ref-board manual */
+       mtdcr(UIC3TR, 0x00ff8c0f);      /* per ref-board manual */
+       mtdcr(UIC3VR, 0x00000001);      /* int31 highest, base=0x000 */
+       mtdcr(UIC3SR, 0xffffffff);      /* clear all */
+
+       mtdcr(UIC0SR, 0xfc000000);      /* clear all */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all */
+       mtdcr(UIC0CR, 0x00000000);      /* all non-critical */
+       mtdcr(UIC0PR, 0xfc000000);      /* */
+       mtdcr(UIC0TR, 0x00000000);      /* */
+       mtdcr(UIC0VR, 0x00000001);      /* */
 
        LED0_ON();
 

diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c
index fc9dfa02c013ac717b36dfacef1d6b7709859f76..01273a1f7db1ea06af686ae379203c05f89ac026 100644 (file)
--- a/board/zeus/zeus.c
+++ b/board/zeus/zeus.c
@@ -50,13 +50,13 @@ static u32 start_time;
 
 int board_early_init_f(void)
 {
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicer, 0x00000000);       /* disable all ints */
-       mtdcr(uiccr, 0x00000000);
-       mtdcr(uicpr, 0xFFFF7F00);       /* set int polarities */
-       mtdcr(uictr, 0x00000000);       /* set int trigger levels */
-       mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
-       mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);
+       mtdcr(UIC0PR, 0xFFFF7F00);      /* set int polarities */
+       mtdcr(UIC0TR, 0x00000000);      /* set int trigger levels */
+       mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
+       mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest priority */
 
        /*
         * Configure CPC0_PCI to enable PerWE as output

diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c
index 3ed15092ae989a00dafb1c91a84b2873c8cb30a8..5e29ff3bcd7ebabbc09bbd55eae9d0fa7ef1b7a3 100644 (file)
--- a/common/cmd_reginfo.c
+++ b/common/cmd_reginfo.c
@@ -93,17 +93,17 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #elif defined (CONFIG_405GP)
        printf ("\n405GP registers; MSR=%08x\n",mfmsr());
        printf ("\nUniversal Interrupt Controller Regs\n"
-           "uicsr    uicer    uiccr    uicpr    uictr    uicmsr   uicvr    uicvcr"
+           "UIC0SR    UIC0ER    UIC0CR    UIC0PR    UIC0TR    UIC0MSR   UIC0VR    UIC0VCR"
            "\n"
            "%08x %08x %08x %08x %08x %08x %08x %08x\n",
-       mfdcr(uicsr),
-       mfdcr(uicer),
-       mfdcr(uiccr),
-       mfdcr(uicpr),
-       mfdcr(uictr),
-       mfdcr(uicmsr),
-       mfdcr(uicvr),
-       mfdcr(uicvcr));
+       mfdcr(UIC0SR),
+       mfdcr(UIC0ER),
+       mfdcr(UIC0CR),
+       mfdcr(UIC0PR),
+       mfdcr(UIC0TR),
+       mfdcr(UIC0MSR),
+       mfdcr(UIC0VR),
+       mfdcr(UIC0VCR));
 
        puts ("\nMemory (SDRAM) Configuration\n"
            "besra    besrsa   besrb    besrsb   bear     mcopt1   rtr      pmit\n");
@@ -180,17 +180,17 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #elif defined(CONFIG_405EP)
        printf ("\n405EP registers; MSR=%08x\n",mfmsr());
        printf ("\nUniversal Interrupt Controller Regs\n"
-           "uicsr    uicer    uiccr    uicpr    uictr    uicmsr   uicvr    uicvcr"
+           "UIC0SR    UIC0ER    UIC0CR    UIC0PR    UIC0TR    UIC0MSR   UIC0VR    UIC0VCR"
            "\n"
            "%08x %08x %08x %08x %08x %08x %08x %08x\n",
-       mfdcr(uicsr),
-       mfdcr(uicer),
-       mfdcr(uiccr),
-       mfdcr(uicpr),
-       mfdcr(uictr),
-       mfdcr(uicmsr),
-       mfdcr(uicvr),
-       mfdcr(uicvcr));
+       mfdcr(UIC0SR),
+       mfdcr(UIC0ER),
+       mfdcr(UIC0CR),
+       mfdcr(UIC0PR),
+       mfdcr(UIC0TR),
+       mfdcr(UIC0MSR),
+       mfdcr(UIC0VR),
+       mfdcr(UIC0VCR));
 
        puts ("\nMemory (SDRAM) Configuration\n"
            "mcopt1   rtr      pmit     mb0cf    mb1cf    sdtr1\n");

diff --git a/cpu/ppc4xx/uic.c b/cpu/ppc4xx/uic.c
index d298b312ceed7963e3a5125645d538374e938a49..8b1b259fafe6b8034b5f13a8cf4b503c4bdb29e7 100644 (file)
--- a/cpu/ppc4xx/uic.c
+++ b/cpu/ppc4xx/uic.c
@@ -109,7 +109,7 @@ void external_interrupt(struct pt_regs *regs)
        /*
         * Read masked interrupt status register to determine interrupt source
         */
-       uic_msr = mfdcr(uic0msr);
+       uic_msr = mfdcr(UIC0MSR);
 
 #if (UIC_MAX > 1)
        if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
@@ -129,7 +129,7 @@ void external_interrupt(struct pt_regs *regs)
                uic_interrupt(UIC3_DCR_BASE, 96);
 #endif
 
-       mtdcr(uic0sr, (uic_msr & UICB0_ALL));
+       mtdcr(UIC0SR, (uic_msr & UICB0_ALL));
 
        if (uic_msr & ~(UICB0_ALL))
                uic_interrupt(UIC0_DCR_BASE, 0);
@@ -140,13 +140,13 @@ void external_interrupt(struct pt_regs *regs)
 void pic_irq_ack(unsigned int vec)
 {
        if ((vec >= 0) && (vec < 32))
-               mtdcr(uicsr, UIC_MASK(vec));
+               mtdcr(UIC0SR, UIC_MASK(vec));
        else if ((vec >= 32) && (vec < 64))
-               mtdcr(uic1sr, UIC_MASK(vec));
+               mtdcr(UIC1SR, UIC_MASK(vec));
        else if ((vec >= 64) && (vec < 96))
-               mtdcr(uic2sr, UIC_MASK(vec));
+               mtdcr(UIC2SR, UIC_MASK(vec));
        else if (vec >= 96)
-               mtdcr(uic3sr, UIC_MASK(vec));
+               mtdcr(UIC3SR, UIC_MASK(vec));
 }
 
 /*
@@ -156,13 +156,13 @@ void pic_irq_enable(unsigned int vec)
 {
 
        if ((vec >= 0) && (vec < 32))
-               mtdcr(uicer, mfdcr(uicer) | UIC_MASK(vec));
+               mtdcr(UIC0ER, mfdcr(UIC0ER) | UIC_MASK(vec));
        else if ((vec >= 32) && (vec < 64))
-               mtdcr(uic1er, mfdcr(uic1er) | UIC_MASK(vec));
+               mtdcr(UIC1ER, mfdcr(UIC1ER) | UIC_MASK(vec));
        else if ((vec >= 64) && (vec < 96))
-               mtdcr(uic2er, mfdcr(uic2er) | UIC_MASK(vec));
+               mtdcr(UIC2ER, mfdcr(UIC2ER) | UIC_MASK(vec));
        else if (vec >= 96)
-               mtdcr(uic3er, mfdcr(uic3er) | UIC_MASK(vec));
+               mtdcr(UIC3ER, mfdcr(UIC3ER) | UIC_MASK(vec));
 
        debug("Install interrupt vector %d\n", vec);
 }
@@ -170,11 +170,11 @@ void pic_irq_enable(unsigned int vec)
 void pic_irq_disable(unsigned int vec)
 {
        if ((vec >= 0) && (vec < 32))
-               mtdcr(uicer, mfdcr(uicer) & ~UIC_MASK(vec));
+               mtdcr(UIC0ER, mfdcr(UIC0ER) & ~UIC_MASK(vec));
        else if ((vec >= 32) && (vec < 64))
-               mtdcr(uic1er, mfdcr(uic1er) & ~UIC_MASK(vec));
+               mtdcr(UIC1ER, mfdcr(UIC1ER) & ~UIC_MASK(vec));
        else if ((vec >= 64) && (vec < 96))
-               mtdcr(uic2er, mfdcr(uic2er) & ~UIC_MASK(vec));
+               mtdcr(UIC2ER, mfdcr(UIC2ER) & ~UIC_MASK(vec));
        else if (vec >= 96)
-               mtdcr(uic3er, mfdcr(uic3er) & ~UIC_MASK(vec));
+               mtdcr(UIC3ER, mfdcr(UIC3ER) & ~UIC_MASK(vec));
 }

diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h
index c908d42452593d158f3813e773f0efbe1674ff39..782d0454b7e5721eb4941af0120870513863bd27 100644 (file)
--- a/include/asm-ppc/ppc4xx-uic.h
+++ b/include/asm-ppc/ppc4xx-uic.h
@@ -1,7 +1,7 @@
 /*
  *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
  *
- * (C) Copyright 2008
+ * (C) Copyright 2008-2009
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -43,7 +43,7 @@
 #define UIC_MAX                1
 #endif
 
-#define IRQ_MAX UIC_MAX * 32
+#define IRQ_MAX                (UIC_MAX * 32)
 
 /*
  * UIC register
@@ -74,53 +74,41 @@
 #define UIC3_DCR_BASE 0xf0
 #endif
 
-#define uic0sr (UIC0_DCR_BASE+0x0)     /* UIC0 status                  */
-#define uic0er (UIC0_DCR_BASE+0x2)     /* UIC0 enable                  */
-#define uic0cr (UIC0_DCR_BASE+0x3)     /* UIC0 critical                */
-#define uic0pr (UIC0_DCR_BASE+0x4)     /* UIC0 polarity                */
-#define uic0tr (UIC0_DCR_BASE+0x5)     /* UIC0 triggering              */
-#define uic0msr (UIC0_DCR_BASE+0x6)    /* UIC0 masked status           */
-#define uic0vr (UIC0_DCR_BASE+0x7)     /* UIC0 vector                  */
-#define uic0vcr (UIC0_DCR_BASE+0x8)    /* UIC0 vector configuration    */
-
-#define uic1sr (UIC1_DCR_BASE+0x0)     /* UIC1 status                  */
-#define uic1er (UIC1_DCR_BASE+0x2)     /* UIC1 enable                  */
-#define uic1cr (UIC1_DCR_BASE+0x3)     /* UIC1 critical                */
-#define uic1pr (UIC1_DCR_BASE+0x4)     /* UIC1 polarity                */
-#define uic1tr (UIC1_DCR_BASE+0x5)     /* UIC1 triggering              */
-#define uic1msr (UIC1_DCR_BASE+0x6)    /* UIC1 masked status           */
-#define uic1vr (UIC1_DCR_BASE+0x7)     /* UIC1 vector                  */
-#define uic1vcr (UIC1_DCR_BASE+0x8)    /* UIC1 vector configuration    */
-
-#define uic2sr (UIC2_DCR_BASE+0x0)     /* UIC2 status-Read Clear       */
-#define uic2srs        (UIC2_DCR_BASE+0x1)     /* UIC2 status-Read Set         */
-#define uic2er (UIC2_DCR_BASE+0x2)     /* UIC2 enable                  */
-#define uic2cr (UIC2_DCR_BASE+0x3)     /* UIC2 critical                */
-#define uic2pr (UIC2_DCR_BASE+0x4)     /* UIC2 polarity                */
-#define uic2tr (UIC2_DCR_BASE+0x5)     /* UIC2 triggering              */
-#define uic2msr (UIC2_DCR_BASE+0x6)    /* UIC2 masked status           */
-#define uic2vr (UIC2_DCR_BASE+0x7)     /* UIC2 vector                  */
-#define uic2vcr (UIC2_DCR_BASE+0x8)    /* UIC2 vector configuration    */
-
-#define uic3sr (UIC3_DCR_BASE+0x0)     /* UIC3 status-Read Clear       */
-#define uic3srs        (UIC3_DCR_BASE+0x1)     /* UIC3 status-Read Set         */
-#define uic3er (UIC3_DCR_BASE+0x2)     /* UIC3 enable                  */
-#define uic3cr (UIC3_DCR_BASE+0x3)     /* UIC3 critical                */
-#define uic3pr (UIC3_DCR_BASE+0x4)     /* UIC3 polarity                */
-#define uic3tr (UIC3_DCR_BASE+0x5)     /* UIC3 triggering              */
-#define uic3msr (UIC3_DCR_BASE+0x6)    /* UIC3 masked status           */
-#define uic3vr (UIC3_DCR_BASE+0x7)     /* UIC3 vector                  */
-#define uic3vcr (UIC3_DCR_BASE+0x8)    /* UIC3 vector configuration    */
-
-/* The following is for compatibility with 405 code */
-#define uicsr  uic0sr
-#define uicer  uic0er
-#define uiccr  uic0cr
-#define uicpr  uic0pr
-#define uictr  uic0tr
-#define uicmsr uic0msr
-#define uicvr  uic0vr
-#define uicvcr uic0vcr
+#define UIC0SR (UIC0_DCR_BASE+0x0)     /* UIC0 status                  */
+#define UIC0ER (UIC0_DCR_BASE+0x2)     /* UIC0 enable                  */
+#define UIC0CR (UIC0_DCR_BASE+0x3)     /* UIC0 critical                */
+#define UIC0PR (UIC0_DCR_BASE+0x4)     /* UIC0 polarity                */
+#define UIC0TR (UIC0_DCR_BASE+0x5)     /* UIC0 triggering              */
+#define UIC0MSR (UIC0_DCR_BASE+0x6)    /* UIC0 masked status           */
+#define UIC0VR (UIC0_DCR_BASE+0x7)     /* UIC0 vector                  */
+#define UIC0VCR (UIC0_DCR_BASE+0x8)    /* UIC0 vector configuration    */
+
+#define UIC1SR (UIC1_DCR_BASE+0x0)     /* UIC1 status                  */
+#define UIC1ER (UIC1_DCR_BASE+0x2)     /* UIC1 enable                  */
+#define UIC1CR (UIC1_DCR_BASE+0x3)     /* UIC1 critical                */
+#define UIC1PR (UIC1_DCR_BASE+0x4)     /* UIC1 polarity                */
+#define UIC1TR (UIC1_DCR_BASE+0x5)     /* UIC1 triggering              */
+#define UIC1MSR (UIC1_DCR_BASE+0x6)    /* UIC1 masked status           */
+#define UIC1VR (UIC1_DCR_BASE+0x7)     /* UIC1 vector                  */
+#define UIC1VCR (UIC1_DCR_BASE+0x8)    /* UIC1 vector configuration    */
+
+#define UIC2SR (UIC2_DCR_BASE+0x0)     /* UIC2 status-Read Clear       */
+#define UIC2ER (UIC2_DCR_BASE+0x2)     /* UIC2 enable                  */
+#define UIC2CR (UIC2_DCR_BASE+0x3)     /* UIC2 critical                */
+#define UIC2PR (UIC2_DCR_BASE+0x4)     /* UIC2 polarity                */
+#define UIC2TR (UIC2_DCR_BASE+0x5)     /* UIC2 triggering              */
+#define UIC2MSR (UIC2_DCR_BASE+0x6)    /* UIC2 masked status           */
+#define UIC2VR (UIC2_DCR_BASE+0x7)     /* UIC2 vector                  */
+#define UIC2VCR (UIC2_DCR_BASE+0x8)    /* UIC2 vector configuration    */
+
+#define UIC3SR (UIC3_DCR_BASE+0x0)     /* UIC3 status-Read Clear       */
+#define UIC3ER (UIC3_DCR_BASE+0x2)     /* UIC3 enable                  */
+#define UIC3CR (UIC3_DCR_BASE+0x3)     /* UIC3 critical                */
+#define UIC3PR (UIC3_DCR_BASE+0x4)     /* UIC3 polarity                */
+#define UIC3TR (UIC3_DCR_BASE+0x5)     /* UIC3 triggering              */
+#define UIC3MSR (UIC3_DCR_BASE+0x6)    /* UIC3 masked status           */
+#define UIC3VR (UIC3_DCR_BASE+0x7)     /* UIC3 vector                  */
+#define UIC3VCR (UIC3_DCR_BASE+0x8)    /* UIC3 vector configuration    */
 
 /*
  * Now the interrupt vector definitions. They are different for most of