riscv: Rename Andes cpu and board names

The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ebc4bef220e648283813e7ef2d7479c4b05ae1e1..48ca4ff4c4ec648dee60af29d37ff9c81dc1e8c8 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -8,8 +8,8 @@ choice
        prompt "Target select"
        optional
 
-config TARGET_AX25_AE350
-       bool "Support ax25-ae350"
+config TARGET_AE350
+       bool "Support ae350"
 
 config TARGET_MICROCHIP_ICICLE
        bool "Support Microchip PolarFire-SoC Icicle Board"
@@ -58,7 +58,7 @@ config SPL_SYS_DCACHE_OFF
          Do not enable data cache in SPL.
 
 # board-specific options below
-source "board/AndesTech/ax25-ae350/Kconfig"
+source "board/AndesTech/ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
 source "board/microchip/mpfs_icicle/Kconfig"
 source "board/sifive/unleashed/Kconfig"
@@ -67,7 +67,7 @@ source "board/openpiton/riscv64/Kconfig"
 source "board/sipeed/maix/Kconfig"
 
 # platform-specific options below
-source "arch/riscv/cpu/ax25/Kconfig"
+source "arch/riscv/cpu/andesv5/Kconfig"
 source "arch/riscv/cpu/fu540/Kconfig"
 source "arch/riscv/cpu/fu740/Kconfig"
 source "arch/riscv/cpu/generic/Kconfig"

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/andesv5/Kconfig
similarity index 100%
rename from arch/riscv/cpu/ax25/Kconfig
rename to arch/riscv/cpu/andesv5/Kconfig

diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/andesv5/Makefile
similarity index 100%
rename from arch/riscv/cpu/ax25/Makefile
rename to arch/riscv/cpu/andesv5/Makefile

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/andesv5/cache.c
similarity index 100%
rename from arch/riscv/cpu/ax25/cache.c
rename to arch/riscv/cpu/andesv5/cache.c

diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
similarity index 100%
rename from arch/riscv/cpu/ax25/cpu.c
rename to arch/riscv/cpu/andesv5/cpu.c

diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/andesv5/spl.c
similarity index 100%
rename from arch/riscv/cpu/ax25/spl.c
rename to arch/riscv/cpu/andesv5/spl.c

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 5c15a0f303a1407217f05c529b3ebd0ee8566902..c576c55767f52b1cc3c107564a0114bed1788622 100644 (file)
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
 dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
 dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb

diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ae350/Kconfig
similarity index 88%
rename from board/AndesTech/ax25-ae350/Kconfig
rename to board/AndesTech/ae350/Kconfig
index 4bb33b07936f7abd3af625351036673967a811d9..75815bf99aa58c62abcb3ea0de80d5196ac5abe5 100644 (file)
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ae350/Kconfig
@@ -1,10 +1,10 @@
-if TARGET_AX25_AE350
+if TARGET_AE350
 
 config SYS_CPU
-       default "ax25"
+       default "andesv5"
 
 config SYS_BOARD
-       default "ax25-ae350"
+       default "ae350"
 
 config SYS_VENDOR
        default "AndesTech"
@@ -13,7 +13,7 @@ config SYS_SOC
        default "ae350"
 
 config SYS_CONFIG_NAME
-       default "ax25-ae350"
+       default "ae350"
 
 config ENV_SIZE
        default 0x2000 if ENV_IS_IN_SPI_FLASH

diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS b/board/AndesTech/ae350/MAINTAINERS
similarity index 80%
rename from board/AndesTech/ax25-ae350/MAINTAINERS
rename to board/AndesTech/ae350/MAINTAINERS
index eebee167c3b63f4cc7db4b344e632236938b4267..ead8e0e2afb61d2c42eafbd876dc9f0ec17b2c28 100644 (file)
--- a/board/AndesTech/ax25-ae350/MAINTAINERS
+++ b/board/AndesTech/ae350/MAINTAINERS
@@ -1,8 +1,8 @@
-AX25-AE350 BOARD
+AE350 BOARD
 M:     Rick Chen <rick@andestech.com>
 S:     Maintained
-F:     board/AndesTech/ax25-ae350/
-F:     include/configs/ax25-ae350.h
+F:     board/AndesTech/ae350/
+F:     include/configs/ae350.h
 F:     configs/ae350_rv32_defconfig
 F:     configs/ae350_rv64_defconfig
 F:     configs/ae350_rv32_xip_defconfig

diff --git a/board/AndesTech/ax25-ae350/Makefile b/board/AndesTech/ae350/Makefile
similarity index 87%
rename from board/AndesTech/ax25-ae350/Makefile
rename to board/AndesTech/ae350/Makefile
index 0e4ba8d702958d8219faff289659f9d0a16ab62e..705ae43af5d4fffdea0a07fe712e97c5fe01f90b 100644 (file)
--- a/board/AndesTech/ax25-ae350/Makefile
+++ b/board/AndesTech/ae350/Makefile
@@ -3,4 +3,4 @@
 # Copyright (C) 2017 Andes Technology Corporation.
 # Rick Chen, Andes Technology Corporation <rick@andestech.com>
 
-obj-y  := ax25-ae350.o
+obj-y  := ae350.o

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ae350/ae350.c
similarity index 100%
rename from board/AndesTech/ax25-ae350/ax25-ae350.c
rename to board/AndesTech/ae350/ae350.c

diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index fd1bf5fa4ff602f7ab7ee055fc1f6bfc2ba4bc57..953cd0700b9097d36f95c7f86e669f2ca2b66b15 100644 (file)
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
 CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80

diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 4d3623a8941b46980dae790557ab0e4d262dc88b..d61f7f5d1d644d4e2d811b2a57d85365f5a25824 100644 (file)
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -8,7 +8,7 @@ CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
 CONFIG_RISCV_SMODE=y
 # CONFIG_AVAILABLE_HARTS is not set
 CONFIG_DISTRO_DEFAULTS=y

diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index a076b77834285a2785561b2910b9305aea32602b..e59ba0c38a9df3f54dcfd281a52c06a9d645d2cc 100644 (file)
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -9,7 +9,7 @@ CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
 CONFIG_RISCV_SMODE=y
 CONFIG_SPL_XIP=y
 CONFIG_DISTRO_DEFAULTS=y

diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
index da1bd2b10b12841274719ccd34c2f5522dc615ad..926632137d6a7853022d827059991fad20139222 100644 (file)
--- a/configs/ae350_rv32_xip_defconfig
+++ b/configs/ae350_rv32_xip_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
 CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
 CONFIG_XIP=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index 959258176af18ba607c679253d1b4ce1e6e19195..3c18562ad4c58134d56361134c999e03681bf498 100644 (file)
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
 CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
 CONFIG_ARCH_RV64I=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y

diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index 0217027e6df1a7437ebfdb4ad2d7de24919ad178..cb69514a7e33dfc3360ac990380dfa672823f689 100644 (file)
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -8,7 +8,7 @@ CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
 # CONFIG_AVAILABLE_HARTS is not set

diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index 5a1fa8b6a151dc9de0dad8db6213a607e02343a1..e0773fa0aaec5c8a93d5ae15fdda65f163b3670f 100644 (file)
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -9,7 +9,7 @@ CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
 CONFIG_SPL=y
 CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
 CONFIG_SPL_XIP=y

diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
index c3fcbf3d28d0b1d1e5bd87e11e7ffb18934f3f5a..0d467b9836c08533067865d0ec090d716f505a6f 100644 (file)
--- a/configs/ae350_rv64_xip_defconfig
+++ b/configs/ae350_rv64_xip_defconfig
@@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
 CONFIG_SYS_PROMPT="RISC-V # "
 CONFIG_SYS_LOAD_ADDR=0x100000
-CONFIG_TARGET_AX25_AE350=y
+CONFIG_TARGET_AE350=y
 CONFIG_ARCH_RV64I=y
 CONFIG_XIP=y
 CONFIG_DISTRO_DEFAULTS=y

diff --git a/doc/board/AndesTech/ax25-ae350.rst b/doc/board/AndesTech/ae350.rst
similarity index 98%
rename from doc/board/AndesTech/ax25-ae350.rst
rename to doc/board/AndesTech/ae350.rst
index b46f427f4b7dcdada02f5b9db643104536a5008a..42a2b4d0b5ee485a395a14f4c052fdbc034ee063 100644 (file)
--- a/doc/board/AndesTech/ax25-ae350.rst
+++ b/doc/board/AndesTech/ae350.rst
@@ -1,20 +1,20 @@
 .. SPDX-License-Identifier: GPL-2.0+
 
-AX25-AE350
-==========
+AE350
+======
 
-AE350 is the mainline SoC produced by Andes Technology using AX25 CPU core
-base on RISC-V architecture.
+AE350 is the mainline SoC produced by Andes Technology using AndesV5 CPU core
+based on RISC-V architecture.
 
 AE350 has integrated both AHB and APB bus and many periphals for application
 and product development.
 
-AX25-AE350 is the SoC with AE350 hardcore CPU.
+AndesV5 is Andes CPU IP family that adopts RISC-V architecture.
 
-AX25 is Andes CPU IP to adopt RISC-V architecture.
+AndesV5 family includes 25, 27, 45 series.
 
-AX25 Features
--------------
+25-Series Features
+------------------
 
 CPU Core
  - 5-stage in-order execution pipeline

diff --git a/doc/board/AndesTech/index.rst b/doc/board/AndesTech/index.rst
index d8f7d155fc26fd679b6223fbce7f2e8b3974380d..cacc5791a91c65a5693e49c454500dbb38bacca0 100644 (file)
--- a/doc/board/AndesTech/index.rst
+++ b/doc/board/AndesTech/index.rst
@@ -7,4 +7,4 @@ Andes Tech
    :maxdepth: 2
 
    adp-ag101p
-   ax25-ae350
+   ae350

diff --git a/include/configs/ax25-ae350.h b/include/configs/ae350.h
similarity index 100%
rename from include/configs/ax25-ae350.h
rename to include/configs/ae350.h