arm: ls1021a: merge SoC specific code in a separate file

Create a soc.c file to put the code for soc special settings.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile
index 2311468ac98ee6a4577a46e1d166a44f06d45585..02283009abd06cfd8fcdaa9c470ef69a21465b37 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -8,6 +8,7 @@ obj-y   += cpu.o
 obj-y  += clock.o
 obj-y  += timer.o
 obj-y  += fsl_epu.o
+obj-y  += soc.o
 
 obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o

diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
new file mode 100644 (file)
index 0000000..0fdd6d4
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <asm/arch/ls102xa_soc.h>
+
+unsigned int get_soc_major_rev(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+       unsigned int svr, major;
+
+       svr = in_be32(&gur->svr);
+       major = SVR_MAJ(svr);
+
+       return major;
+}
+
+int arch_soc_init(void)
+{
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+       unsigned int major;
+
+#ifdef CONFIG_FSL_QSPI
+       out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
+#endif
+
+#ifdef CONFIG_FSL_DCU_FB
+       out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+#endif
+
+       /* Configure Little endian for SAI, ASRC and SPDIF */
+       out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
+
+       /*
+        * Enable snoop requests and DVM message requests for
+        * Slave insterface S4 (A7 core cluster)
+        */
+       out_le32(&cci->slave[4].snoop_ctrl,
+                CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+       major = get_soc_major_rev();
+       if (major == SOC_MAJOR_VER_1_0) {
+               /*
+                * Set CCI-400 Slave interface S1, S2 Shareable Override
+                * Register All transactions are treated as non-shareable
+                */
+               out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+               out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
+               /* Workaround for the issue that DDR could not respond to
+                * barrier transaction which is generated by executing DSB/ISB
+                * instruction. Set CCI-400 control override register to
+                * terminate the barrier transaction. After DDR is initialized,
+                * allow barrier transaction to DDR again */
+               out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+       }
+
+       return 0;
+}

diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
new file mode 100644 (file)
index 0000000..f10cb91
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __FSL_LS102XA_SOC_H
+#define __FSL_LS102XA_SOC_H
+
+unsigned int get_soc_major_rev(void);
+int arch_soc_init(void);
+#endif /* __FSL_LS102XA_SOC_H */

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index d889ad50fd04d83d88197234c9fc70f6d0ac35bd..be3358a564a8195b5ed3b511f34e200dd878f0e8 100644 (file)
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -11,6 +11,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ls102xa_stream_id.h>
+#include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_devdis.h>
 #include <asm/arch/ls102xa_sata.h>
 #include <hwconfig.h>
@@ -140,17 +141,6 @@ unsigned long get_board_ddr_clk(void)
        return 66666666;
 }
 
-unsigned int get_soc_major_rev(void)
-{
-       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-       unsigned int svr, major;
-
-       svr = in_be32(&gur->svr);
-       major = SVR_MAJ(svr);
-
-       return major;
-}
-
 int select_i2c_ch_pca9547(u8 ch)
 {
        int ret;
@@ -193,8 +183,6 @@ int board_mmc_init(bd_t *bis)
 int board_early_init_f(void)
 {
        struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-       unsigned int major;
 
 #ifdef CONFIG_TSEC_ENET
        /* clear BD & FR bits for BE BD's and frame data */
@@ -205,40 +193,7 @@ int board_early_init_f(void)
        init_early_memctl_regs();
 #endif
 
-#ifdef CONFIG_FSL_QSPI
-       out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
-#endif
-
-#ifdef CONFIG_FSL_DCU_FB
-       out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
-#endif
-
-       /* Configure Little endian for SAI, ASRC and SPDIF */
-       out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
-
-       /*
-        * Enable snoop requests and DVM message requests for
-        * Slave insterface S4 (A7 core cluster)
-        */
-       out_le32(&cci->slave[4].snoop_ctrl,
-                CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
-
-       major = get_soc_major_rev();
-       if (major == SOC_MAJOR_VER_1_0) {
-               /*
-                * Set CCI-400 Slave interface S1, S2 Shareable Override
-                * Register All transactions are treated as non-shareable
-                */
-               out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-               out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-
-               /* Workaround for the issue that DDR could not respond to
-                * barrier transaction which is generated by executing DSB/ISB
-                * instruction. Set CCI-400 control override register to
-                * terminate the barrier transaction. After DDR is initialized,
-                * allow barrier transaction to DDR again */
-               out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
-       }
+       arch_soc_init();
 
 #if defined(CONFIG_DEEP_SLEEP)
        if (is_warm_boot())

diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index 4918c1192e2bd268cd6fd748853971445c049c77..8eaff5f0cedf2d2fec4ec254c34c5af93e71f758 100644 (file)
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -12,6 +12,7 @@
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ls102xa_stream_id.h>
 #include <asm/arch/ls102xa_devdis.h>
+#include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_sata.h>
 #include <hwconfig.h>
 #include <mmc.h>
@@ -138,17 +139,6 @@ int checkboard(void)
        return 0;
 }
 
-unsigned int get_soc_major_rev(void)
-{
-       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
-       unsigned int svr, major;
-
-       svr = in_be32(&gur->svr);
-       major = SVR_MAJ(svr);
-
-       return major;
-}
-
 void ddrmc_init(void)
 {
        struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
@@ -394,8 +384,6 @@ conflict:
 int board_early_init_f(void)
 {
        struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-       unsigned int major;
 
 #ifdef CONFIG_TSEC_ENET
        /* clear BD & FR bits for BE BD's and frame data */
@@ -407,33 +395,7 @@ int board_early_init_f(void)
        init_early_memctl_regs();
 #endif
 
-#ifdef CONFIG_FSL_DCU_FB
-       out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
-#endif
-
-#ifdef CONFIG_FSL_QSPI
-       out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
-#endif
-
-       /* Configure Little endian for SAI, ASRC and SPDIF */
-       out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
-
-       /*
-        * Enable snoop requests and DVM message requests for
-        * Slave insterface S4 (A7 core cluster)
-        */
-       out_le32(&cci->slave[4].snoop_ctrl,
-                CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
-
-       major = get_soc_major_rev();
-       if (major == SOC_MAJOR_VER_1_0) {
-               /*
-                * Set CCI-400 Slave interface S1, S2 Shareable Override
-                * Register All transactions are treated as non-shareable
-                */
-               out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-               out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-       }
+       arch_soc_init();
 
 #if defined(CONFIG_DEEP_SLEEP)
        if (is_warm_boot()) {