dm: gpio: Add driver for stm32f7 gpio controller

This patch adds gpio driver supporting driver model for stm32f7 gpio.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Christophe KERELLO <christophe.kerello@st.com>
[trini: Add depends on STM32]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/include/asm/arch-stm32f7/gpio.h b/arch/arm/include/asm/arch-stm32f7/gpio.h
index 2942cd923c09189b3b1f7d70dbb05d8c938e2007..45999b4d2e34761083ae094fa5e0680053f9cb46 100644 (file)
--- a/arch/arm/include/asm/arch-stm32f7/gpio.h
+++ b/arch/arm/include/asm/arch-stm32f7/gpio.h
@@ -96,6 +96,22 @@ struct stm32_gpio_ctl {
        enum stm32_gpio_af      af;
 };
 
+struct stm32_gpio_regs {
+       u32 moder;      /* GPIO port mode */
+       u32 otyper;     /* GPIO port output type */
+       u32 ospeedr;    /* GPIO port output speed */
+       u32 pupdr;      /* GPIO port pull-up/pull-down */
+       u32 idr;        /* GPIO port input data */
+       u32 odr;        /* GPIO port output data */
+       u32 bsrr;       /* GPIO port bit set/reset */
+       u32 lckr;       /* GPIO port configuration lock */
+       u32 afr[2];     /* GPIO alternate function */
+};
+
+struct stm32_gpio_priv {
+       struct stm32_gpio_regs *regs;
+};
+
 static inline unsigned stm32_gpio_to_port(unsigned gpio)
 {
        return gpio / 16;
@@ -106,8 +122,4 @@ static inline unsigned stm32_gpio_to_pin(unsigned gpio)
        return gpio % 16;
 }
 
-int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc,
-               const struct stm32_gpio_ctl *gpio_ctl);
-int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state);
-
 #endif /* _STM32_GPIO_H_ */

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c95e9acd5f73a7383036469c24e02e3af2a66f56..99516119ff1d2486c1ef902d7a060aa35a004bfc 100644 (file)
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -171,6 +171,15 @@ config PIC32_GPIO
        help
          Say yes here to support Microchip PIC32 GPIOs.
 
+config STM32F7_GPIO
+       bool "ST STM32 GPIO driver"
+       depends on DM_GPIO && STM32
+       default y
+       help
+         Device model driver support for STM32 GPIO controller. It should be
+         usable on many stm32 families like stm32f4 & stm32H7.
+         Tested on STM32F7.
+
 config MVEBU_GPIO
        bool "Marvell MVEBU GPIO driver"
        depends on DM_GPIO && ARCH_MVEBU

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 27f8068e3e60da10cd4a78dd8ebaaf2b9ef9173c..0ca845f54caa6bcc1111e44ad591eb7016de9429 100644 (file)
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -49,6 +49,7 @@ oby-$(CONFIG_SX151X)          += sx151x.o
 obj-$(CONFIG_SUNXI_GPIO)       += sunxi_gpio.o
 obj-$(CONFIG_LPC32XX_GPIO)     += lpc32xx_gpio.o
 obj-$(CONFIG_STM32_GPIO)       += stm32_gpio.o
+obj-$(CONFIG_STM32F7_GPIO)     += stm32f7_gpio.o
 obj-$(CONFIG_GPIO_UNIPHIER)    += gpio-uniphier.o
 obj-$(CONFIG_ZYNQ_GPIO)                += zynq_gpio.o
 obj-$(CONFIG_VYBRID_GPIO)      += vybrid_gpio.o

diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32f7_gpio.c
new file mode 100644 (file)
index 0000000..5e05463
--- /dev/null
+++ b/drivers/gpio/stm32f7_gpio.c
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2017
+ * Vikas Manocha, <vikas.manocha@st.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/stm32.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+#define MAX_SIZE_BANK_NAME             5
+#define STM32_GPIOS_PER_BANK           16
+#define MODE_BITS(gpio_pin)            (gpio_pin * 2)
+#define MODE_BITS_MASK                 3
+#define IN_OUT_BIT_INDEX(gpio_pin)     (1UL << (gpio_pin))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+       struct stm32_gpio_priv *priv = dev_get_priv(dev);
+       struct stm32_gpio_regs *regs = priv->regs;
+       int bits_index = MODE_BITS(offset);
+       int mask = MODE_BITS_MASK << bits_index;
+
+       clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_IN << bits_index);
+
+       return 0;
+}
+
+static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
+                                      int value)
+{
+       struct stm32_gpio_priv *priv = dev_get_priv(dev);
+       struct stm32_gpio_regs *regs = priv->regs;
+       int bits_index = MODE_BITS(offset);
+       int mask = MODE_BITS_MASK << bits_index;
+
+       clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
+       mask = IN_OUT_BIT_INDEX(offset);
+       clrsetbits_le32(&regs->odr, mask, value ? mask : 0);
+
+       return 0;
+}
+
+static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+       struct stm32_gpio_priv *priv = dev_get_priv(dev);
+       struct stm32_gpio_regs *regs = priv->regs;
+
+       return readl(&regs->idr) & IN_OUT_BIT_INDEX(offset) ? 1 : 0;
+}
+
+static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
+{
+       struct stm32_gpio_priv *priv = dev_get_priv(dev);
+       struct stm32_gpio_regs *regs = priv->regs;
+       int mask = IN_OUT_BIT_INDEX(offset);
+
+       clrsetbits_le32(&regs->odr, mask, value ? mask : 0);
+
+       return 0;
+}
+
+static const struct dm_gpio_ops gpio_stm32_ops = {
+       .direction_input        = stm32_gpio_direction_input,
+       .direction_output       = stm32_gpio_direction_output,
+       .get_value              = stm32_gpio_get_value,
+       .set_value              = stm32_gpio_set_value,
+};
+
+static int gpio_stm32_probe(struct udevice *dev)
+{
+       struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+       struct stm32_gpio_priv *priv = dev_get_priv(dev);
+       fdt_addr_t addr;
+       char *name;
+
+       addr = dev_get_addr(dev);
+       if (addr == FDT_ADDR_T_NONE)
+               return -EINVAL;
+
+       priv->regs = (struct stm32_gpio_regs *)addr;
+       name = (char *)fdtdec_locate_byte_array(gd->fdt_blob,
+                                               dev_of_offset(dev),
+                                               "st,bank-name",
+                                               MAX_SIZE_BANK_NAME);
+       if (!name)
+               return -EINVAL;
+       uc_priv->bank_name = name;
+       uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
+       debug("%s, addr = 0x%p, bank_name = %s\n", __func__, (u32 *)priv->regs,
+             uc_priv->bank_name);
+
+#ifdef CONFIG_CLK
+       struct clk clk;
+       int ret;
+       ret = clk_get_by_index(dev, 0, &clk);
+       if (ret < 0)
+               return ret;
+
+       ret = clk_enable(&clk);
+
+       if (ret) {
+               dev_err(dev, "failed to enable clock\n");
+               return ret;
+       }
+       debug("clock enabled for device %s\n", dev->name);
+#endif
+
+       return 0;
+}
+
+static const struct udevice_id stm32_gpio_ids[] = {
+       { .compatible = "st,stm32-gpio" },
+       { }
+};
+
+U_BOOT_DRIVER(gpio_stm32) = {
+       .name   = "gpio_stm32",
+       .id     = UCLASS_GPIO,
+       .of_match = stm32_gpio_ids,
+       .probe  = gpio_stm32_probe,
+       .ops    = &gpio_stm32_ops,
+       .flags  = DM_FLAG_PRE_RELOC | DM_UC_FLAG_SEQ_ALIAS,
+       .priv_auto_alloc_size   = sizeof(struct stm32_gpio_priv),
+};

diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index aa2c440b14301b86169cc65594ad3707d64f4029..0e74d051c30475d2903a4acbcb7289c0a5a724de 100644 (file)
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -1,10 +1,45 @@
 #include <common.h>
-#include <asm/arch/gpio.h>
 #include <dm.h>
 #include <dm/pinctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define MODE_BITS_MASK                 3
+#define OSPEED_MASK                    3
+#define PUPD_MASK                      3
+#define OTYPE_MSK                      1
+#define AFR_MASK                       0xF
+
+static int stm32_gpio_config(struct gpio_desc *desc,
+                            const struct stm32_gpio_ctl *ctl)
+{
+       struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
+       struct stm32_gpio_regs *regs = priv->regs;
+       u32 index;
+
+       if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
+           ctl->pupd > 2 || ctl->speed > 3)
+               return -EINVAL;
+
+       index = (desc->offset & 0x07) * 4;
+       clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index,
+                       ctl->af << index);
+
+       index = desc->offset * 2;
+       clrsetbits_le32(&regs->moder, MODE_BITS_MASK << index,
+                       ctl->mode << index);
+       clrsetbits_le32(&regs->ospeedr, OSPEED_MASK << index,
+                       ctl->speed << index);
+       clrsetbits_le32(&regs->pupdr, PUPD_MASK << index, ctl->pupd << index);
+
+       index = desc->offset;
+       clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index);
+
+       return 0;
+}
 static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
 {
        gpio_dsc->port = (port_pin & 0xF000) >> 12;
@@ -18,6 +53,7 @@ static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
 static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
 {
        gpio_fn &= 0x00FF;
+       gpio_ctl->af = 0;
 
        switch (gpio_fn) {
        case 0: