Drop all duplicate newlines from config headers.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
#define CFG_SYS_CS0_MASK 0x007F0001
#define CFG_SYS_CS0_CTRL 0x00001FA0
-
#endif /* _M5208EVBE_H */
# define CFG_SYS_CS0_CTRL 0x00001D80
#endif
-
#endif /* _M5329EVB_H */
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
-
#endif /* M5249 */
#define CFG_SYS_UART_PORT (0)
-
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
#define CFG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
#define CFG_SYS_GPIO1_LED 0x00400000 /* user led */
-
#endif /* _M5253DEMO_H */
#define CFG_SYS_PBDAT 0x0000
#define CFG_SYS_PDCNT 0x00000000
-
#endif /* _M5272C3_H */
#define CFG_SYS_CS1_CTRL 0x00001900
#define CFG_SYS_CS1_MASK 0x00070001
-
#endif /* _M5275EVB_H */
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
-
#endif /* _CONFIG_M5282EVB_H */
#define CFG_SYS_CS1_MASK 0x00070001
#define CFG_SYS_CS1_CTRL 0x00001FA0
-
#endif /* _M53017EVB_H */
#define CFG_SYS_CS2_CTRL 0x00001f60
#endif
-
#endif /* _M5329EVB_H */
#define CFG_SYS_CS2_MASK (16 << 20)
#define CFG_SYS_CS2_CTRL 0x00001f60
-
#endif /* _M5373EVB_H */
*/
#define CFG_SYS_NAND_BASE 0xE0600000
-
/* Vitesse 7385 */
#define CFG_SYS_VSC7385_BASE 0xF0000000
/* I2C */
-
/*
* RapidIO
*/
#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
-
#define __USB_PHY_TYPE utmi
/*
#define CFG_SYS_BAUDRATE_TABLE \
{ 9600, 14400, 19200, 38400, 57600, 115200, 230400, 380400, 460800, 921600 }
-
/* Default environemnt variables */
#define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80400000\0" \
"stdin=serial\0" \
#include "mx6_common.h"
-
/* MMC Configs */
#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \
CF_CACR_DCM_P)
-
#endif /* _CONFIG_ASTRO_MCF5373L_H */
#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */
#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */
-
#endif /* _CONFIG_COBRA5272_H */
"run tftp_mmc_rootfs;" \
"run tftp_mmc_rootfs_bkp;" \
-
#define TFTP_UPDATE_RECOVERY_SWU_KERNEL \
"tftp_sf_fitImg_SWU=" \
"if tftp ${loadaddr} ${kernel_file}; then " \
"tftpboot ${loadaddr} u-boot-with-spl.kwb; " \
"sf update ${loadaddr} 0x0 0xd0000\0"
-
/* increase autoneg timeout, my NIC sucks */
#endif /* _CONFIG_SYNOLOGY_DS414_H */
#define CFG_SYS_DDRUA 0x05
#define CFG_SYS_PJPAR 0xFF
-
#endif /* _CONFIG_M5282EVB_H */
/*---------------------------------------------------------------------*/
/* 512kB on-chip NOR flash */
# define CFG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
-
/* bootstrap + u-boot + env + linux in dataflash on CS0 */
/* NAND flash */
"run doboot; " \
"run failbootcmd\0" \
-
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CFG_SYS_FSL_USDHC_NUM 2
-
/* Ethernet Configs */
#define CFG_FEC_MXC_PHYADDR 0
#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CFG_SYS_FSL_USDHC_NUM 2
-
/* USB Configs */
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x200000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x200000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
/* Totally 6GB DDR */
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
/* Totally 6GB or 4G DDR */
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x100000000 /* 4 GiB DDR */
#ifdef CONFIG_SPL_BUILD
#define CFG_MALLOC_F_ADDR 0x22040000
-
#endif
/* ENET Config */
#define CFG_SYS_INIT_RAM_ADDR 0x80000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
-
#endif /* __CONFIG_J721E_EVM_H */
#define CFG_MALLOC_F_ADDR 0x182000
/* For RAW image gives a error info not panic */
-
#define CFG_POWER_PFUZE100_I2C_ADDR 0x08
#endif
ENV_MEM_LAYOUT_SETTINGS \
BOOTENV
-
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
*/
#define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
-
/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR 0x40
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$board\0"
-
#ifdef CONFIG_TFABOOT
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt;"
/* I2C */
-
/* Serial Port */
#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
#define QIXIS_BASE_PHYS 0x20000000
#define QIXIS_BASE_PHYS_EARLY 0xC000000
-
#define CFG_SYS_NAND_BASE 0x530000000ULL
#define CFG_SYS_NAND_BASE_PHYS 0x30000000
-
/* MC firmware */
/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
#define CFG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
#define SPD_EEPROM_ADDRESS 0x51
-
/*
* IFC Definitions
*/
#define SPD_EEPROM_ADDRESS 0x51
-
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
#define CFG_SYS_NOR0_CSPR_EXT (0x0)
#define CFG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
* will be udpated later when get_bus_freq(0) is available.
*/
-
/* Serial Port */
#define CFG_PL011_CLOCK (get_bus_freq(0) / 4)
#define CFG_SYS_SERIAL0 0x21c0000
BOOTENV
#endif
-
#endif /* __MESON64_CONFIG_H */
#include <linux/sizes.h>
-
#define CFG_SYS_NS16550_COM1 0x11005200
#define CFG_SYS_NS16550_CLK 26000000
#include <linux/sizes.h>
-
#define CFG_SYS_NS16550_COM1 0x11005000
#define CFG_SYS_NS16550_CLK 26000000
/* bootz: zImage/initrd.img support */
-
/* USB Configs */
#define CFG_MXC_USB_PORT 1
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#ifndef __MX6ULLEVK_CONFIG_H
#define __MX6ULLEVK_CONFIG_H
-
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include <linux/stringify.h>
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-
/* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE SZ_512K
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE SZ_512K
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#ifndef __PICO_IMX6UL_CONFIG_H
#define __PICO_IMX6UL_CONFIG_H
-
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#include "mx6_common.h"
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x80000
-
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */
"name=userdata,size=4820M,uuid=${uuid_gpt_userdata};" \
"name=rootfs,size=-,uuid=" ROOT_UUID
-
#include <configs/meson64_android.h>
#endif /* __CONFIG_H */
#define CFG_SYS_NS16550_COM1 0x44e09000
#define CFG_SYS_NS16550_COM4 0x481a6000
-
/* I2C Configuration */
/* Defines for SPL */
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
-
/* Hardcoded values, to use instead of SPD */
#define CFG_SYS_DDR_CS0_BNDS 0x0000000f
#define CFG_SYS_DDR_CS0_CONFIG 0x80010102
"update_sf=run dh_update_sd_to_sf\0" \
"usb_pgood_delay=1000\0"
-
#include <configs/stm32mp15_common.h>
#endif
#define CACR_STATUS (CFG_SYS_INIT_RAM_ADDR + \
CFG_SYS_INIT_RAM_SIZE - 12)
-
#define CFG_SYS_I2C_0
#endif /* __STMARK2_CONFIG_H */
#include "ls1088a_common.h"
-
#define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd"
#ifndef __CONFIG_TOPIC_MIAMI_H
#define __CONFIG_TOPIC_MIAMI_H
-
/* Speed up boot time by ignoring the environment which we never used */
#include "zynq-common.h"
#define CFG_SYS_FSL_USDHC_NUM 1
-
#define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
/* USB Device Firmware Update support */
"ramdisk_addr_r=0x4000000\0" \
"ramdiskfile=initramfs.gz\0"
-
#endif /* __CONFIG_H */
/* U-Boot autoboot configuration */
/*==============================*/
-
/*=========================================*/
/* FPGA Registers (board info and control) */
/*=========================================*/
#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
#define CFG_SYS_INIT_RAM_SIZE 0x2000
-
/* Extend size of kernel image for uncompression */
/* Address in RAM where the parameters must be copied by SPL. */