]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
configs: Remove duplicate newlines
authorMarek Vasut <marek.vasut+renesas@mailbox.org>
Sun, 16 Jun 2024 15:19:11 +0000 (17:19 +0200)
committerTom Rini <trini@konsulko.com>
Fri, 5 Jul 2024 19:57:01 +0000 (13:57 -0600)
Drop all duplicate newlines from config headers.
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
63 files changed:
include/configs/M5208EVBE.h
include/configs/M5235EVB.h
include/configs/M5249EVB.h
include/configs/M5253DEMO.h
include/configs/M5272C3.h
include/configs/M5275EVB.h
include/configs/M5282EVB.h
include/configs/M53017EVB.h
include/configs/M5329EVB.h
include/configs/M5373EVB.h
include/configs/MPC837XERDB.h
include/configs/P2041RDB.h
include/configs/T4240RDB.h
include/configs/arbel.h
include/configs/aristainetos2.h
include/configs/astro_mcf5373l.h
include/configs/cobra5272.h
include/configs/display5.h
include/configs/ds414.h
include/configs/eb_cpu5282.h
include/configs/ethernut5.h
include/configs/ge_bx50v3.h
include/configs/imx6_logic.h
include/configs/imx7-cm.h
include/configs/imx8mm-cl-iot-gate.h
include/configs/imx8mm_evk.h
include/configs/imx8mn_evk.h
include/configs/imx8mp_evk.h
include/configs/imx8mp_rsb3720.h
include/configs/imx8mq_cm.h
include/configs/imx8mq_evk.h
include/configs/imx8mq_phanbell.h
include/configs/imx8mq_reform2.h
include/configs/imx8ulp_evk.h
include/configs/j721e_evm.h
include/configs/kontron_pitx_imx8m.h
include/configs/ls1012aqds.h
include/configs/ls1043a_common.h
include/configs/ls1088a_common.h
include/configs/ls1088aqds.h
include/configs/ls1088ardb.h
include/configs/lx2160a_common.h
include/configs/meson64.h
include/configs/mt8183.h
include/configs/mt8516.h
include/configs/mx53cx9020.h
include/configs/mx6ullevk.h
include/configs/mx7ulp_evk.h
include/configs/phycore_imx8mm.h
include/configs/phycore_imx8mp.h
include/configs/pico-imx6ul.h
include/configs/pico-imx8mq.h
include/configs/sei510.h
include/configs/siemens-am33x-common.h
include/configs/socrates.h
include/configs/stm32mp15_dh_dhsom.h
include/configs/stmark2.h
include/configs/ten64.h
include/configs/topic_miami.h
include/configs/warp7.h
include/configs/x86-common.h
include/configs/xtfpga.h
include/configs/zynq-common.h

index d4c1e0668845cf784062f1df356b2b94b477fa33..a4fda551f1f736e913c1e3d0b93737e559962cf1 100644 (file)
 #define CFG_SYS_CS0_MASK               0x007F0001
 #define CFG_SYS_CS0_CTRL               0x00001FA0
 
-
 #endif                         /* _M5208EVBE_H */
index e54281834007abe88ff459313b747e9533b15b8f..8939c8e7ab9c3cd71ecb4a281d45d669e0580672 100644 (file)
 #      define CFG_SYS_CS0_CTRL 0x00001D80
 #endif
 
-
 #endif                         /* _M5329EVB_H */
index 2f4743ce50cf7dbd6bc4427b0ccf867af3c823d6..4fd539c0174969086b351c32e8d4a849d80e8636 100644 (file)
 #define        CFG_SYS_GPIO1_OUT               0x00c70000      /* Set outputs to default state */
 #define CFG_SYS_GPIO1_LED              0x00400000      /* user led                     */
 
-
 #endif /* M5249 */
index 0ff0bfce90b09f9cd9b228d2d3d1e56fcede94d8..75c70be7ac4def554b1560665fcc9d5d5aa70574 100644 (file)
@@ -10,7 +10,6 @@
 
 #define CFG_SYS_UART_PORT              (0)
 
-
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
  */
 #define CFG_SYS_GPIO1_OUT              0x00c70000      /* Set outputs to default state */
 #define CFG_SYS_GPIO1_LED              0x00400000      /* user led */
 
-
 #endif                         /* _M5253DEMO_H */
index 98a17181a41efead383c8d91b461b166c6ea9e56..0d332cba61c29a16316141277c2ab7709fe8cd3b 100644 (file)
 #define CFG_SYS_PBDAT          0x0000
 #define CFG_SYS_PDCNT          0x00000000
 
-
 #endif                         /* _M5272C3_H */
index 77ddf717643304655e2b8fff934890583ce5b399..607c5dee2fb0b44de478c1336c34debf0a03e8fd 100644 (file)
 #define CFG_SYS_CS1_CTRL               0x00001900
 #define CFG_SYS_CS1_MASK               0x00070001
 
-
 #endif /* _M5275EVB_H */
index e289a23b8008ee4c8e8f39984c6f688114e1e499..31699a40b6f7a206c8a0227e9336fc5d44cb075d 100644 (file)
 #define CFG_SYS_DDRUA          0x05
 #define CFG_SYS_PJPAR          0xFF
 
-
 #endif                         /* _CONFIG_M5282EVB_H */
index dcc5701ee0bcd4521d8b2450fb4515b527644782..6359915e09a657555807e853d1e3b7264debd60e 100644 (file)
 #define CFG_SYS_CS1_MASK               0x00070001
 #define CFG_SYS_CS1_CTRL               0x00001FA0
 
-
 #endif                         /* _M53017EVB_H */
index dd5d4c980233099e12e60ae87f1cad4acb14499d..456135bdc64a84891aa7ac33c422f4fb31626e23 100644 (file)
 #define CFG_SYS_CS2_CTRL               0x00001f60
 #endif
 
-
 #endif                         /* _M5329EVB_H */
index 4bb99487509fa939b912648078bac40ebe9da0ed..4e8dcb5ef7f7161a5556c11d26b97f457cec0205 100644 (file)
 #define CFG_SYS_CS2_MASK               (16 << 20)
 #define CFG_SYS_CS2_CTRL               0x00001f60
 
-
 #endif                         /* _M5373EVB_H */
index 3967cc283631c7f2745d5f122ae83871c4463dc3..a5176d176dc8dd614a70721099c90ab846a27d3f 100644 (file)
  */
 #define CFG_SYS_NAND_BASE      0xE0600000
 
-
 /* Vitesse 7385 */
 
 #define CFG_SYS_VSC7385_BASE   0xF0000000
index 28f53ae78a1cc99ac969fe37fe435f210fce1afa..7cf6514f14872bcd09316b0ddee2811dd2d42cde 100644 (file)
 
 /* I2C */
 
-
 /*
  * RapidIO
  */
index 78e136224ec53f54b7577a4fd12f1930c0c82b55..c95325e162d19aa67529a0191875ee3d249979a8 100644 (file)
 #define CFG_SYS_FSL_ESDHC_ADDR       CFG_SYS_MPC85xx_ESDHC_ADDR
 #endif
 
-
 #define __USB_PHY_TYPE utmi
 
 /*
index d8ccc4596823b194ed14423829404db5495c0f8d..61f6a5e2438d3f281f89a234e9ca0e212a00dad0 100644 (file)
@@ -15,7 +15,6 @@
 #define CFG_SYS_BAUDRATE_TABLE \
        { 9600, 14400, 19200, 38400, 57600, 115200, 230400, 380400, 460800, 921600 }
 
-
 /* Default environemnt variables */
 #define CFG_EXTRA_ENV_SETTINGS   "uimage_flash_addr=80400000\0"   \
                "stdin=serial\0"   \
index 286435d6f84cf6a505853236a12ac1ff94a460da..9d4a4bbdf43ca21fd7b9e2c58ac325941ecc9ef7 100644 (file)
@@ -22,7 +22,6 @@
 
 #include "mx6_common.h"
 
-
 /* MMC Configs */
 #define CFG_SYS_FSL_ESDHC_ADDR      USDHC1_BASE_ADDR
 
index f3bfefa835e4d6e58a054d0a1f4beffbcc693428..65224324fbc216041317ac1d92cdc6e17c2c4084 100644 (file)
 #define CFG_SYS_CACHE_ICACR            (CF_CACR_EC | CF_CACR_CINVA | \
                                         CF_CACR_DCM_P)
 
-
 #endif /* _CONFIG_ASTRO_MCF5373L_H */
index 556705fb09f7894c52275ea27438474932fad959..cd50ffe98d0dfb0c516acf36929facd062ee170b 100644 (file)
@@ -184,5 +184,4 @@ configuration */
 #define CFG_SYS_PBDAT          0x0000                  /* PortB value reg. */
 #define CFG_SYS_PDCNT          0x00000000              /* PortD control reg. */
 
-
 #endif /* _CONFIG_COBRA5272_H */
index 3b96fff7d6f81ded88c0c99225a3fae901f676de..2005a256d6e35023eebcb748d71ec68180d07f39 100644 (file)
        "run tftp_mmc_rootfs;" \
        "run tftp_mmc_rootfs_bkp;" \
 
-
 #define TFTP_UPDATE_RECOVERY_SWU_KERNEL \
        "tftp_sf_fitImg_SWU=" \
            "if tftp ${loadaddr} ${kernel_file}; then " \
index f1921dac5e7647ddd01a30bb9b4a2d1ce35b4ca0..6fbcec0898af826adb7d96ce703729f29c3f452e 100644 (file)
@@ -53,7 +53,6 @@
                "tftpboot ${loadaddr} u-boot-with-spl.kwb; "    \
                "sf update ${loadaddr} 0x0 0xd0000\0"
 
-
 /* increase autoneg timeout, my NIC sucks */
 
 #endif /* _CONFIG_SYNOLOGY_DS414_H */
index e2c9d9c43cee579f60bf400452bf8cd646a12814..26e4ade34ee724315f99891706de774f83bdb5dc 100644 (file)
 #define CFG_SYS_DDRUA          0x05
 #define CFG_SYS_PJPAR          0xFF
 
-
 #endif /* _CONFIG_M5282EVB_H */
 /*---------------------------------------------------------------------*/
index 182369def910c1a530060f9acf3de927e15876e5..807c6963192f10aefb3ba4fe5a16bcbf6b6dc38d 100644 (file)
@@ -32,7 +32,6 @@
 /* 512kB on-chip NOR flash */
 # define CFG_SYS_FLASH_BASE            0x00200000 /* AT91SAM9XE_FLASH_BASE */
 
-
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 
 /* NAND flash */
index 32960fb93256f39a06cf0781a580036b4a05e013..07b36706e56d4490ec45dca8298de7b1b69be97e 100644 (file)
@@ -88,7 +88,6 @@
                "run doboot; " \
                "run failbootcmd\0" \
 
-
 /* Physical Memory Map */
 #define PHYS_SDRAM                     MMDC0_ARB_BASE_ADDR
 
index 85c054451f35cb22affbacfb51ef12700fdbbe8d..66004a6eb2a362e37678f2e62077e2ae9cb86abe 100644 (file)
@@ -17,7 +17,6 @@
 #define CFG_SYS_FSL_ESDHC_ADDR      0
 #define CFG_SYS_FSL_USDHC_NUM       2
 
-
 /* Ethernet Configs */
 #define CFG_FEC_MXC_PHYADDR         0
 
index 106fbdb9053c4694a2bdc11fa1a6fac7c4f5a3ca..131f18290b900204eb23069cb4be696eb46267c8 100644 (file)
@@ -77,7 +77,6 @@
 #define CFG_SYS_FSL_ESDHC_ADDR       USDHC1_BASE_ADDR
 #define CFG_SYS_FSL_USDHC_NUM          2
 
-
 /* USB Configs */
 #define CFG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
 
index 0c547027ba69013a2093b82b0faf026ade6f9c7c..6442e3d570f4a1740645f5d9b0393d6d026e1896 100644 (file)
 #define CFG_SYS_INIT_RAM_ADDR  0x40000000
 #define CFG_SYS_INIT_RAM_SIZE  0x80000
 
-
 #define CFG_SYS_SDRAM_BASE             0x40000000
 #define PHYS_SDRAM                     0x40000000
 #define PHYS_SDRAM_SIZE                        0x80000000 /* 2GB DDR */
index d5642b96495f34b978140e3d166c24cf02197769..9dd63fc11961060b4af0a8608f9446660b62a37b 100644 (file)
@@ -56,7 +56,6 @@
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
 #define CFG_SYS_INIT_RAM_SIZE        0x200000
 
-
 #define CFG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE                        0x80000000 /* 2GB DDR */
index b759b834b808ff4c6dc8b619175ece10c6101289..ca02e26c26e42f7606be4e17f77ccf25bdcf9bd1 100644 (file)
@@ -48,7 +48,6 @@
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
 #define CFG_SYS_INIT_RAM_SIZE        0x200000
 
-
 #define CFG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE                        0x80000000 /* 2GB DDR */
index 71452aa28332f78bba75ee09924fc3464bb00f0c..741ee39db1a340136b57d9411d96bca995e0ebd2 100644 (file)
@@ -43,7 +43,6 @@
 #define CFG_SYS_INIT_RAM_ADDR  0x40000000
 #define CFG_SYS_INIT_RAM_SIZE  0x80000
 
-
 /* Totally 6GB DDR */
 #define CFG_SYS_SDRAM_BASE             0x40000000
 #define PHYS_SDRAM                     0x40000000
index 10a166d781edc119736924511bd7a122b48ec657..b82e35f49631f3e67f5825c4c1b4d8a6130c46ce 100644 (file)
 #define CFG_SYS_INIT_RAM_ADDR  0x40000000
 #define CFG_SYS_INIT_RAM_SIZE  0x80000
 
-
 /* Totally 6GB or 4G DDR */
 #define CFG_SYS_SDRAM_BASE             0x40000000
 #define PHYS_SDRAM                     0x40000000
index 7cf482d6de159e5ae65dbeb750e25bf449813911..2bbd6b1680ffcd19402985fd338fc159bfbfd6a8 100644 (file)
@@ -48,7 +48,6 @@
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
 #define CFG_SYS_INIT_RAM_SIZE        0x80000
 
-
 #define CFG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE                                        0x40000000 /* 1 GB DDR */
index d2e1649400a7ad37f7ce678d552aff5c4ec2dde2..9eefc31dc6ffea20dd36270530b94c1814e218e3 100644 (file)
@@ -53,7 +53,6 @@
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
 #define CFG_SYS_INIT_RAM_SIZE        0x80000
 
-
 #define CFG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE                        0xC0000000 /* 3GB DDR */
index b66fc18fa5e84923b7c4e23cabe5d20bbb7b1c3c..cd73a72d2b7ea9e29e64a10f9cdb45e2d856e04c 100644 (file)
@@ -86,7 +86,6 @@
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
 #define CFG_SYS_INIT_RAM_SIZE        0x80000
 
-
 #define CFG_SYS_SDRAM_BASE           0x40000000
 #define PHYS_SDRAM                      0x40000000
 #define PHYS_SDRAM_SIZE                        0x40000000 /* 1GB DDR */
index 3148e8622e1c1a0c0fc5f1caf1634123e3b9da9d..7fa441a8a838d76d6bc5e597bd1ef58f7be023f6 100644 (file)
@@ -54,7 +54,6 @@
 #define CFG_SYS_INIT_RAM_ADDR          0x40000000
 #define CFG_SYS_INIT_RAM_SIZE          0x80000
 
-
 #define CFG_SYS_SDRAM_BASE             0x40000000
 #define PHYS_SDRAM                     0x40000000
 #define PHYS_SDRAM_SIZE                        0x100000000     /* 4 GiB DDR */
index 750aef1b597e279c315afe1ee2d0dd93b0e00136..aa9da19a11f720dab97ed9e5247ce7bb6e3ec989 100644 (file)
@@ -14,7 +14,6 @@
 #ifdef CONFIG_SPL_BUILD
 #define CFG_MALLOC_F_ADDR              0x22040000
 
-
 #endif
 
 /* ENET Config */
@@ -51,7 +50,6 @@
 #define CFG_SYS_INIT_RAM_ADDR  0x80000000
 #define CFG_SYS_INIT_RAM_SIZE  0x80000
 
-
 #define CFG_SYS_SDRAM_BASE             0x80000000
 #define PHYS_SDRAM                     0x80000000
 #define PHYS_SDRAM_SIZE                        0x80000000 /* 2GB DDR */
index a5140ea6a1156ba677f42f9a2440a2647b83a7db..bdf12ee8f7e30671784ec71866414f176ab8a29f 100644 (file)
@@ -54,5 +54,4 @@
 /* Now for the remaining common defines */
 #include <configs/ti_armv7_common.h>
 
-
 #endif /* __CONFIG_J721E_EVM_H */
index 101c59141f743b80ce168ef2c550d4aa909a1934..3dda7b668064f00d93f08c205d15f80cb2dbcfb7 100644 (file)
@@ -18,7 +18,6 @@
 #define CFG_MALLOC_F_ADDR              0x182000
 /* For RAW image gives a error info not panic */
 
-
 #define CFG_POWER_PFUZE100_I2C_ADDR  0x08
 #endif
 
@@ -56,7 +55,6 @@
        ENV_MEM_LAYOUT_SETTINGS \
        BOOTENV
 
-
 #define CFG_SYS_INIT_RAM_ADDR        0x40000000
 #define CFG_SYS_INIT_RAM_SIZE        0x80000
 
index 35e8ff057986578a34387205fc3f48cd62b9dfcc..3c4f8b75b18e2f2cf2dc98d9a58c689df9fc0986 100644 (file)
@@ -48,7 +48,6 @@
 */
 #define CFG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 
-
 /* Voltage monitor on channel 2*/
 #define I2C_VOL_MONITOR_ADDR           0x40
 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
index ac2319c1b42b1d346dbd3286cc5cf2ba8da49c7a..e500a7d80ff7a5e732ef84cbd672eae72071efad 100644 (file)
                " && esbc_validate ${kernelheader_addr_r};"     \
                "bootm $load_addr#$board\0"
 
-
 #ifdef CONFIG_TFABOOT
 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "  \
                           "env exists secureboot && esbc_halt;"
index 720a95d2f5394dcea14872c02ad9297d0e27701c..34085eeecc7da4b7b4c9c247f003b262ca1ae700 100644 (file)
@@ -42,7 +42,6 @@
 
 /* I2C */
 
-
 /* Serial Port */
 #define CFG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
 
@@ -84,11 +83,9 @@ unsigned long long get_qixis_addr(void);
 #define QIXIS_BASE_PHYS                                0x20000000
 #define QIXIS_BASE_PHYS_EARLY                  0xC000000
 
-
 #define CFG_SYS_NAND_BASE                      0x530000000ULL
 #define CFG_SYS_NAND_BASE_PHYS         0x30000000
 
-
 /* MC firmware */
 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
 #define CFG_SYS_LS_MC_DPC_MAX_LENGTH       0x20000
index 084ee064ae685b79198249a4be93cb401cbc6982..36e8422c34da9cd5a3d8fc3a17050ce1b89121fc 100644 (file)
@@ -16,7 +16,6 @@
 
 #define SPD_EEPROM_ADDRESS             0x51
 
-
 /*
  * IFC Definitions
  */
index a1749149e505c46238d9f1fa39f8137a9956805e..8be5febe57b65b275602e015d6d67e0beb69c696 100644 (file)
@@ -17,7 +17,6 @@
 
 #define SPD_EEPROM_ADDRESS     0x51
 
-
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 #define CFG_SYS_NOR0_CSPR_EXT  (0x0)
 #define CFG_SYS_NOR_AMASK              IFC_AMASK(128 * 1024 * 1024)
index 6f46ca78d4d834f56692ac66f3bfec3a614e0446..4c1b4bf2b2c32fb1ffd7b390e16c29ba7004ad98 100644 (file)
@@ -37,7 +37,6 @@
  * will be udpated later when get_bus_freq(0) is available.
  */
 
-
 /* Serial Port */
 #define CFG_PL011_CLOCK                (get_bus_freq(0) / 4)
 #define CFG_SYS_SERIAL0                0x21c0000
index 65fa5f3d6dd574f92f01baeb840b300e0bcd28ab..ccb8ea2e7169c2972a16a9c66bb6d6e2bf911f0a 100644 (file)
        BOOTENV
 #endif
 
-
 #endif /* __MESON64_CONFIG_H */
index 1f973829bba4d81111612f8fcfba304ef0369930..7c31e219afd212afdc710ce415d4e06866194c11 100644 (file)
@@ -11,7 +11,6 @@
 
 #include <linux/sizes.h>
 
-
 #define CFG_SYS_NS16550_COM1           0x11005200
 #define CFG_SYS_NS16550_CLK            26000000
 
index 73776e3705b778407a6512be04dcf84ff86fe31a..27c3718352d0e45f0b31dd395464b3d568c674a1 100644 (file)
@@ -11,7 +11,6 @@
 
 #include <linux/sizes.h>
 
-
 #define CFG_SYS_NS16550_COM1           0x11005000
 #define CFG_SYS_NS16550_CLK            26000000
 
index e995776d30d5e2aafda41df25b44b1c6abb58386..dccfdc3a15dac76d51f22ef4ab39ab16a8069a35 100644 (file)
@@ -21,7 +21,6 @@
 
 /* bootz: zImage/initrd.img support */
 
-
 /* USB Configs */
 #define CFG_MXC_USB_PORT       1
 #define CFG_MXC_USB_PORTSC     (PORT_PTS_UTMI | PORT_PTS_PTW)
index 2c3cd32cefa70b24a2ed6fd529bddd498f021e57..910140ab4b708c833be0eb1aaccb6beabd4d66c9 100644 (file)
@@ -7,7 +7,6 @@
 #ifndef __MX6ULLEVK_CONFIG_H
 #define __MX6ULLEVK_CONFIG_H
 
-
 #include <asm/arch/imx-regs.h>
 #include <linux/sizes.h>
 #include <linux/stringify.h>
index 5f4cd93062315f7f947ec552ecbfe95c890f6dff..d1c1202d06135bf1f1d3b49666fb819ab978326c 100644 (file)
@@ -11,7 +11,6 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
-
 /* Using ULP WDOG for reset */
 #define WDOG_BASE_ADDR                 WDG1_RBASE
 
index ce6dc87c69c71a0e1dc17713927048a24588f4fa..dd7cfdba52d2b00b3aaabaca884fb84f9235732e 100644 (file)
@@ -63,7 +63,6 @@
 #define CFG_SYS_INIT_RAM_ADDR  0x40000000
 #define CFG_SYS_INIT_RAM_SIZE  SZ_512K
 
-
 #define CFG_SYS_SDRAM_BASE             0x40000000
 
 #define PHYS_SDRAM                     0x40000000
index 299fabc6a99bcb1410b926851b20a0e3ce3bbb19..47c56b50b1633ffa3ef5a3ff1d2dd0c7ff749cbf 100644 (file)
@@ -18,7 +18,6 @@
 #define CFG_SYS_INIT_RAM_ADDR  0x40000000
 #define CFG_SYS_INIT_RAM_SIZE  SZ_512K
 
-
 #define CFG_SYS_SDRAM_BASE             0x40000000
 
 #define PHYS_SDRAM                     0x40000000
index 4caa823375831215d95c6fcd31be66b2cd0aa255..8a22f0134b398bc8945207628f7915406e3ead49 100644 (file)
@@ -7,7 +7,6 @@
 #ifndef __PICO_IMX6UL_CONFIG_H
 #define __PICO_IMX6UL_CONFIG_H
 
-
 #include <asm/arch/imx-regs.h>
 #include <linux/sizes.h>
 #include "mx6_common.h"
index be31f8a23cab23128042a14587b7657e57834a55..422b89a3dd3509d7eac2283b6c907b5d40d8d5f1 100644 (file)
@@ -65,7 +65,6 @@
 #define CFG_SYS_INIT_RAM_ADDR  0x40000000
 #define CFG_SYS_INIT_RAM_SIZE  0x80000
 
-
 #define CFG_SYS_SDRAM_BASE             0x40000000
 #define PHYS_SDRAM                     0x40000000
 #define PHYS_SDRAM_SIZE                        0x80000000      /* 2 GiB DDR */
index ea91a0615771bf8b2bb8981f78affd048a83b68a..0f8070b8d317ca60ce92aacba59abf23fe87c92d 100644 (file)
@@ -25,7 +25,6 @@
        "name=userdata,size=4820M,uuid=${uuid_gpt_userdata};" \
        "name=rootfs,size=-,uuid=" ROOT_UUID
 
-
 #include <configs/meson64_android.h>
 
 #endif /* __CONFIG_H */
index 6b1d5caafb19ed97fa4c4401781a83401a2b4c4a..74b7fe85800f4c5242b08612ae132931fcbf9fa4 100644 (file)
@@ -40,7 +40,6 @@
 #define CFG_SYS_NS16550_COM1           0x44e09000
 #define CFG_SYS_NS16550_COM4           0x481a6000
 
-
 /* I2C Configuration */
 
 /* Defines for SPL */
index 64cc17ca7ca2d25e7b31cd0dc83654df515490f2..006d649f6ed654cc3b6afc51c661f353408e0167 100644 (file)
@@ -48,7 +48,6 @@
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS     0x50    /* CTLR 0 DIMM 0 */
 
-
 /* Hardcoded values, to use instead of SPD */
 #define CFG_SYS_DDR_CS0_BNDS           0x0000000f
 #define CFG_SYS_DDR_CS0_CONFIG         0x80010102
index c1fca8359d217bdc941cc900644114cc8afa697b..6fe6e7b9b8ca61a8984ac1969d580b52df937ae8 100644 (file)
@@ -53,7 +53,6 @@
        "update_sf=run dh_update_sd_to_sf\0"                            \
        "usb_pgood_delay=1000\0"
 
-
 #include <configs/stm32mp15_common.h>
 
 #endif
index af5da096b7d3767c4fd6f4f1295a0b7fc143ab4b..c8a39e191a21d8a1f6d6d699acdf030be011e8f5 100644 (file)
@@ -95,7 +95,6 @@
 #define CACR_STATUS                    (CFG_SYS_INIT_RAM_ADDR + \
                                        CFG_SYS_INIT_RAM_SIZE - 12)
 
-
 #define CFG_SYS_I2C_0
 
 #endif /* __STMARK2_CONFIG_H */
index d2bef9b6e528d8b8bd8b9eb2dc3221924cef8b57..d5bb2e96c51a2e655f3b490545e6f1890178489b 100644 (file)
@@ -9,7 +9,6 @@
 
 #include "ls1088a_common.h"
 
-
 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 
 #define QSPI_NOR_BOOTCOMMAND   "run distro_bootcmd"
index 3795e6152fa9b3df6429f04fdd2f20310f60f596..06276175455092cacf29cd1f3eb1f253eece5be8 100644 (file)
@@ -9,7 +9,6 @@
 #ifndef __CONFIG_TOPIC_MIAMI_H
 #define __CONFIG_TOPIC_MIAMI_H
 
-
 /* Speed up boot time by ignoring the environment which we never used */
 
 #include "zynq-common.h"
index 5d2956a5963c9bcbd7e6dc5a014ee72434c0f223..0da9250c3b7899f0c3f5c3bedc9f0a0df7f5c010 100644 (file)
@@ -92,7 +92,6 @@
 
 #define CFG_SYS_FSL_USDHC_NUM  1
 
-
 #define CFG_MXC_USB_PORTSC             (PORT_PTS_UTMI | PORT_PTS_PTW)
 
 /* USB Device Firmware Update support */
index 8bd0716c08d2fd81da7a5de49e4762211041c7a2..d93a45d5aae221b945ff6caa37eb393d7e637f5e 100644 (file)
@@ -36,5 +36,4 @@
        "ramdisk_addr_r=0x4000000\0"                    \
        "ramdiskfile=initramfs.gz\0"
 
-
 #endif /* __CONFIG_H */
index 9655b666eda71a4ae354ee712b15c3649c51c9e4..468c5b85ab7c474775c4ef7d9327e2b296d7746b 100644 (file)
@@ -71,7 +71,6 @@
 /* U-Boot autoboot configuration */
 /*==============================*/
 
-
 /*=========================================*/
 /* FPGA Registers (board info and control) */
 /*=========================================*/
index 553bb1b45b69baa4852d2149a9fbad7d53bf587e..03af859c951084a2b0a2a84e511ff1528c08037c 100644 (file)
 #define CFG_SYS_INIT_RAM_ADDR  0xFFFF0000
 #define CFG_SYS_INIT_RAM_SIZE  0x2000
 
-
 /* Extend size of kernel image for uncompression */
 
 /* Address in RAM where the parameters must be copied by SPL. */