]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig
authorLey Foon Tan <ley.foon.tan@intel.com>
Wed, 5 Apr 2017 09:32:51 +0000 (17:32 +0800)
committerMarek Vasut <marex@denx.de>
Fri, 14 Apr 2017 12:06:57 +0000 (14:06 +0200)
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
arch/arm/mach-socfpga/Kconfig
drivers/Kconfig
drivers/ddr/Kconfig [new file with mode: 0644]
drivers/ddr/altera/Kconfig [new file with mode: 0644]
drivers/ddr/altera/Makefile
include/configs/socfpga_common.h

index 18bb6dce3c86c18d6dfcb68c70968b13f184bb09..9bfee04098cc307952e872afdac6c3350ce0bd22 100644 (file)
@@ -43,6 +43,7 @@ config TARGET_SOCFPGA_CYCLONE5
 
 config TARGET_SOCFPGA_GEN5
        bool
+       select ALTERA_SDRAM
 
 choice
        prompt "Altera SOCFPGA board select"
index 0e5d97d166464f3cb77dfff635353dc9d74d1ddc..3e6bbacd15c0064ae7cc67903e522227543c89c4 100644 (file)
@@ -14,6 +14,8 @@ source "drivers/cpu/Kconfig"
 
 source "drivers/crypto/Kconfig"
 
+source "drivers/ddr/Kconfig"
+
 source "drivers/demo/Kconfig"
 
 source "drivers/ddr/fsl/Kconfig"
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
new file mode 100644 (file)
index 0000000..b764add
--- /dev/null
@@ -0,0 +1 @@
+source "drivers/ddr/altera/Kconfig"
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
new file mode 100644 (file)
index 0000000..021ec1d
--- /dev/null
@@ -0,0 +1,5 @@
+config ALTERA_SDRAM
+       bool "SoCFPGA DDR SDRAM driver"
+       depends on TARGET_SOCFPGA_GEN5
+       help
+         Enable DDR SDRAM controller for the SoCFPGA devices.
index 1ca705856d2b354a31243c7fe5ac2f82426ff706..bdd28722a98a638b078f73e678c8309f2fb82604 100644 (file)
@@ -8,4 +8,6 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o
+ifdef CONFIG_ALTERA_SDRAM
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o
+endif
index 8057b8847562c5e20483adbe4ca069714755b9e9..d4d72fa91d583ba3a4c95940d48591fba4d15535 100644 (file)
 #define CONFIG_SYS_L2_PL310
 #define CONFIG_SYS_PL310_BASE          SOCFPGA_MPUL2_ADDRESS
 
-/*
- * SDRAM controller
- */
-#define CONFIG_ALTERA_SDRAM
-
 /*
  * EPCS/EPCQx1 Serial Flash Controller
  */