riscv: complete the list of exception codes

Only the first four exception codes are defined. Add the missing
exception codes from the definition in RISC-V Privileged Architecture
Version 1.10.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 62a16b4da9f61e80cd4f9a9eba21f5e5c863f33f..6a12818c2b225aaea183489820930eedf0ec0103 100644 (file)
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -67,7 +67,18 @@ static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
                "Instruction access fault",
                "Illegal instruction",
                "Breakpoint",
-               "Load address misaligned"
+               "Load address misaligned",
+               "Load access fault",
+               "Store/AMO address misaligned",
+               "Store/AMO access fault",
+               "Environment call from U-mode",
+               "Environment call from S-mode",
+               "Reserved",
+               "Environment call from M-mode",
+               "Instruction page fault",
+               "Load page fault",
+               "Reserved",
+               "Store/AMO page fault",
        };
 
        printf("exception code: %ld , %s , epc %lx , ra %lx\n",