arm64: zynqmp: Setup clock for DP and DPDMA

Clocks are coming from shared HW design where these frequencies should be
aligned with PLL setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/04454c50d0d13e450976942085d763ab5aa38f98.1645629459.git.michal.simek@xilinx.com

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 664e65896d7e8aded297209950ca575a44de13b7..86b99070c4a8fe0c181c8b87aa3d90c98c559c82 100644 (file)
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -279,10 +279,14 @@
 
 &zynqmp_dpdma {
        clocks = <&zynqmp_clk DPDMA_REF>;
+       assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
 };
 
 &zynqmp_dpsub {
        clocks = <&zynqmp_clk TOPSW_LSBUS>,
                 <&zynqmp_clk DP_AUDIO_REF>,
                 <&zynqmp_clk DP_VIDEO_REF>;
+       assigned-clocks = <&zynqmp_clk DP_STC_REF>,
+                         <&zynqmp_clk DP_AUDIO_REF>,
+                         <&zynqmp_clk DP_VIDEO_REF>;  /* rpll, rpll, vpll */
 };

diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
index 22602d8c33f84c46db4830965af9ddc0d200bcf3..34fb592d4fa51d1658ae40e6d26d7264ecc62344 100644 (file)
--- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -115,10 +115,12 @@
        status = "disabled";
        phy-names = "dp-phy0", "dp-phy1";
        phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+       assigned-clock-rates = <27000000>, <25000000>, <300000000>;
 };
 
 &zynqmp_dpdma {
        status = "okay";
+       assigned-clock-rates = <600000000>;
 };
 
 &usb0 {

diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
index 01b14ebcb609a1093e23c05745f346a34fa966a2..35247b0bbd2e30cfb84d018151a9865659a9716c 100644 (file)
--- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -95,10 +95,12 @@
        status = "disabled";
        phy-names = "dp-phy0", "dp-phy1";
        phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+       assigned-clock-rates = <27000000>, <25000000>, <300000000>;
 };
 
 &zynqmp_dpdma {
        status = "okay";
+       assigned-clock-rates = <600000000>;
 };
 
 &usb0 {