arm: vf610: add DDR_SEL_PAD_CONTR register

Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM
issues with newer silicon (1.1). This register was added in revision
4 of the Vybrid Reference Manual.

Signed-off-by: Stefan Agner <stefan@agner.ch>

diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index c2f976184664872567f7f8f019a7f43ccb1ccc11..0c28e1b8403a4f52a89c1e26117ea5a558323b23 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -215,6 +215,7 @@
 #define DDRMC_CR139_PHY_WRLV_EN(v)                     ((v) & 0xff)
 #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v)       (((v) & 0x1f) << 27)
 #define DDRMC_CR154_PAD_ZQ_MODE(v)                     (((v) & 0x3) << 21)
+#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v)               (((v) & 0x3) << 18)
 #define DDRMC_CR155_AXI0_AWCACHE                       (1 << 10)
 #define DDRMC_CR155_PAD_ODT_BYTE1(v)                   ((v) & 0x7)
 #define DDRMC_CR158_TWR(v)                             ((v) & 0x3f)

diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index 4ee74c019883785b5cf14df09a5fc19b48e6cabb..d64d3aa872205f237fce290ae4ec0187c1ead705 100644 (file)
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -217,7 +217,8 @@ void ddr_ctrl_init(void)
                &ddrmr->cr[139]);
 
        writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
-               DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
+               DDRMC_CR154_PAD_ZQ_MODE(1) |
+               DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]);
        writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
                &ddrmr->cr[155]);
        writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);