fix: phy: marvell: cp110: rename comphy_index to cp_index

No functional change.
The variable name "comphy_index" is misleading, it represents
cp index and not comphy index.

Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/drivers/phy/marvell/comphy.h b/drivers/phy/marvell/comphy.h
index 8b05757e912a6cfdfbd88a0c84e2cacea735ad60..c9b94a4c5e3c02fcd28055962ca308302aec1dfd 100644 (file)
--- a/drivers/phy/marvell/comphy.h
+++ b/drivers/phy/marvell/comphy.h
@@ -97,7 +97,7 @@ struct chip_serdes_phy_config {
        void __iomem *hpipe3_base_addr;
        u32 comphy_lanes_count;
        u32 comphy_mux_bitcount;
-       u32 comphy_index;
+       u32 cp_index;
 };
 
 /* Register helper functions */

diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index ab0b2a800cfca42c7ef419db64cfccda67bcb650..596921b6c3304415b835c472817e792d7d94fd9a 100644 (file)
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -174,13 +174,13 @@ static int comphy_probe(struct udevice *dev)
                lane++;
        }
 
-       /* Save comphy index for MultiCP devices (A8K) */
-       chip_cfg->comphy_index = current_idx++;
+       /* Save CP index for MultiCP devices (A8K) */
+       chip_cfg->cp_index = current_idx++;
        /* PHY power UP sequence */
        chip_cfg->ptr_comphy_chip_init(chip_cfg, comphy_map_data);
        /* PHY print SerDes status */
        if (of_machine_is_compatible("marvell,armada8040"))
-               printf("Comphy chip #%d:\n", chip_cfg->comphy_index);
+               printf("Comphy chip #%d:\n", chip_cfg->cp_index);
        comphy_print(chip_cfg, comphy_map_data);
 
        /*
@@ -189,7 +189,7 @@ static int comphy_probe(struct udevice *dev)
        if (of_machine_is_compatible("marvell,armada8040"))
                last_idx = 1;
 
-       if (chip_cfg->comphy_index == last_idx) {
+       if (chip_cfg->cp_index == last_idx) {
                /* Initialize dedicated PHYs (not muxed SerDes lanes) */
                comphy_dedicated_phys_init();
        }

diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index 21de90c3a1dbbf4d23816110be7669f9ba240100..df605712394891c037bf6d1ee4886601629bace8 100644 (file)
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -582,7 +582,7 @@ static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
 }
 
 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
-                               void __iomem *comphy_base, int comphy_index)
+                               void __iomem *comphy_base, int cp_index)
 {
        u32 mask, data, i, ret = 1;
        void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
@@ -601,7 +601,7 @@ static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
         * In order to parse each CPs SATA node, fdt_node_offset_by_compatible
         * must be called again (according to the CP id)
         */
-       for (i = 0; i < (comphy_index + 1); i++)
+       for (i = 0; i < (cp_index + 1); i++)
                sata_node = fdt_node_offset_by_compatible(
                        gd->fdt_blob, sata_node, "marvell,armada-8k-ahci");
 
@@ -1947,7 +1947,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
                case PHY_TYPE_SATA3:
                        ret = comphy_sata_power_up(
                                lane, hpipe_base_addr, comphy_base_addr,
-                               ptr_chip_cfg->comphy_index);
+                               ptr_chip_cfg->cp_index);
                        break;
                case PHY_TYPE_USB3_HOST0:
                case PHY_TYPE_USB3_HOST1: