clk: renesas: Fix swapped div and mul in debug output on Gen2

The $div and $mul values were swapped in the debug output,
fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index aedaab723bfa30c472cca56b9cfa51e95e33fa27..34abe784fdd4ee4ca4428a9ab3af12bb956eb166 100644 (file)
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -121,7 +121,7 @@ static ulong gen2_clk_get_rate(struct clk *clk)
 
        case CLK_TYPE_FF:
                rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
-               debug("%s[%i] FIXED clk: parent=%i div=%i mul=%i => rate=%u\n",
+               debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
                      __func__, __LINE__,
                      core->parent, core->mult, core->div, rate);
                return rate;