ddr: imx8m: Add DRAM PLL to generate 1000Mhz output

We will generate DRAM 4000MT/s as default for i.MX8MP.
So need DRAM PLL to generate 1000Mhz clock to DDR PHY and controller.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c
index 863fb4389714ce34ad0ef36d9f09988012258e28..9ac7ca923c7b2f3201097e811decbf31a0354dd1 100644 (file)
--- a/drivers/ddr/imx/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c
@@ -106,6 +106,10 @@ int wait_ddrphy_training_complete(void)
 void ddrphy_init_set_dfi_clk(unsigned int drate)
 {
        switch (drate) {
+       case 4000:
+               dram_pll_init(MHZ(1000));
+               dram_disable_bypass();
+               break;
        case 3200:
                dram_pll_init(MHZ(800));
                dram_disable_bypass();