clk: rk3588: Add 742.5M parameter for PLL

For a specific frequency.

Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index 119b1337bdf2bbcc4f037ca062dce037034aac35..c861762641471c5c2d4700c63ba178d0b93f36a1 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -36,6 +36,7 @@ static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
        RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
        RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
        RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
+       RK3588_PLL_RATE(742500000, 4, 495, 2, 0),
        RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
        RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
        RK3588_PLL_RATE(594000000, 2, 198, 2, 0),