board: synquacer: set actual gd->ram_top and gd->ram_size

Current gd->ram_size and gd->ram_top reflect only the
first DRAM bank even if the SynQuacer Developerbox could
have up to three DRAM banks.
With the commit 06d514d77c37 ("lmb: consider EFI memory map"),
the first DRAM bank indicates <4GB address, so whole >4GB memory
is marked as EFI_BOOT_SERVICES_DATA and it results that
U-Boot can not access >4GB memory.

Since 64-bits DRAM address is fully available on the SynQuacer
Developerbox, let's set the installed DIMM information to
gd->ram_top and gd->ram_size.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>

diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c
index 204e5a41a5b767881eb2a4e9c0f048ba130b4941..9585944d80c154dcad71e2e946e5bdf74f24f635 100644 (file)
--- a/board/socionext/developerbox/developerbox.c
+++ b/board/socionext/developerbox/developerbox.c
@@ -145,13 +145,27 @@ int dram_init(void)
 {
        struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
        struct draminfo_entry *ent = synquacer_draminfo->entry;
+       unsigned long size = 0;
+       int i;
+
+       for (i = 0; i < synquacer_draminfo->nr_regions; i++)
+               size += ent[i].size;
 
-       gd->ram_size = ent[0].size;
+       gd->ram_size = size;
        gd->ram_base = ent[0].base;
 
        return 0;
 }
 
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
+{
+       struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;
+       struct draminfo_entry *ent = synquacer_draminfo->entry;
+
+       return ent[synquacer_draminfo->nr_regions - 1].base +
+              ent[synquacer_draminfo->nr_regions - 1].size;
+}
+
 int dram_init_banksize(void)
 {
        struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE;