video: stm32: stm32_ltdc: fix the check of return value of clk_set_rate()

The clk_set_rate() function returns rate as an 'ulong' not
an 'int' and rate > 0 by default.

This patch avoids to display the associated warning when
the set rate function returns the new frequency.

Fixes: aeaf330649e8 ("video: stm32: stm32_ltdc: add bridge to display controller")
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 87e5fd54d9a801c55bdd5a4edf177589544c589e..e741e74739c10a5f34340b93f0cc04f18af51da3 100644 (file)
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -338,6 +338,7 @@ static int stm32_ltdc_probe(struct udevice *dev)
        struct display_timing timings;
        struct clk pclk;
        struct reset_ctl rst;
+       ulong rate;
        int ret;
 
        priv->regs = (void *)dev_read_addr(dev);
@@ -375,13 +376,13 @@ static int stm32_ltdc_probe(struct udevice *dev)
                }
        }
 
-       ret = clk_set_rate(&pclk, timings.pixelclock.typ);
-       if (ret)
-               dev_warn(dev, "fail to set pixel clock %d hz\n",
-                        timings.pixelclock.typ);
+       rate = clk_set_rate(&pclk, timings.pixelclock.typ);
+       if (IS_ERR_VALUE(rate))
+               dev_warn(dev, "fail to set pixel clock %d hz, ret=%ld\n",
+                        timings.pixelclock.typ, rate);
 
        dev_dbg(dev, "Set pixel clock req %d hz get %ld hz\n",
-               timings.pixelclock.typ, clk_get_rate(&pclk));
+               timings.pixelclock.typ, rate);
 
        ret = reset_get_by_index(dev, 0, &rst);
        if (ret) {