riscv: align mtvec on a 4-byte boundary

The machine trap-vector base address (mtvec) must be aligned on a 4-byte
boundary. Add the necessary align directive to trap_entry.

This patch also removes the global directive for trap_entry, which is
not required.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bd5904500ccac091ff09f0331dc4180dddfc1eb2..88b4aaa1c0e9454aef2663abdd6963ce1ea41b32 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -42,7 +42,6 @@ nmi_vector:
 trap_vector:
        j       trap_entry
 
-.global trap_entry
 handle_reset:
        li      t0, CONFIG_SYS_SDRAM_BASE
        SREG    a2, 0(t0)
@@ -208,6 +207,7 @@ call_board_init_r:
 /*
  * trap entry
  */
+.align 2
 trap_entry:
        addi    sp, sp, -32*REGBYTES
        SREG    x1, 1*REGBYTES(sp)