arm: dts: imx8mm-cl-iot-gate: add Compulab's ied overlays

add the following overlays:
 - IED extension board
 - CAN/TPM/ADC extension board on IED board.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 75ea7e8e3758e717a72f6e68058115455d05c9a6..cd24d7ee8d66c1b7ad79cc7b3e628429bb73d0b0 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1178,9 +1178,23 @@ dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
 
 dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
 
-dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
-
-dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb
+dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb \
+                                       imx8mm-cl-iot-gate-ied.dtbo \
+                                       imx8mm-cl-iot-gate-ied-adc0.dtbo \
+                                       imx8mm-cl-iot-gate-ied-adc1.dtbo \
+                                       imx8mm-cl-iot-gate-ied-can0.dtbo \
+                                       imx8mm-cl-iot-gate-ied-can1.dtbo \
+                                       imx8mm-cl-iot-gate-ied-tpm0.dtbo \
+                                       imx8mm-cl-iot-gate-ied-tpm1.dtbo
+
+dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb \
+                                       imx8mm-cl-iot-gate-ied.dtbo \
+                                       imx8mm-cl-iot-gate-ied-adc0.dtbo \
+                                       imx8mm-cl-iot-gate-ied-adc1.dtbo \
+                                       imx8mm-cl-iot-gate-ied-can0.dtbo \
+                                       imx8mm-cl-iot-gate-ied-can1.dtbo \
+                                       imx8mm-cl-iot-gate-ied-tpm0.dtbo \
+                                       imx8mm-cl-iot-gate-ied-tpm1.dtbo
 
 dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
 

diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dts
new file mode 100644 (file)
index 0000000..3f2201e
--- /dev/null
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc0.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+       vref_adc: regulator-vref-adc {
+               compatible = "regulator-fixed";
+               regulator-name = "vref_adc";
+               regulator-min-microvolt = <2400000>;
+               regulator-max-microvolt = <2400000>;
+               regulator-always-on;
+       };
+};
+
+&ecspi2 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       adc0: adc@0 {
+               compatible = "maxim,max11108";
+               reg = <0>;
+               vref-supply = <&vref_adc>;
+               spi-max-frequency = <20000000>;
+               status = "okay";
+       };
+};

diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dts
new file mode 100644 (file)
index 0000000..bb0f848
--- /dev/null
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied-adc1.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+       vref_adc: regulator-vref-adc {
+               compatible = "regulator-fixed";
+               regulator-name = "vref_adc";
+               regulator-min-microvolt = <2400000>;
+               regulator-max-microvolt = <2400000>;
+               regulator-always-on;
+       };
+};
+
+&ecspi3 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       adc1: adc@0 {
+               compatible = "maxim,max11108";
+               reg = <0>;
+               vref-supply = <&vref_adc>;
+               spi-max-frequency = <20000000>;
+               status = "okay";
+       };
+};

diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dts
new file mode 100644 (file)
index 0000000..0e46300
--- /dev/null
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied-can0.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "imx8mm-pinfunc.h"
+
+&{/} {
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clk40m: clk@1 {
+                       compatible = "fixed-clock";
+                       reg = <1>;
+                       #clock-cells = <0>;
+                       clock-frequency = <40000000>;
+                       clock-output-names = "clk40m";
+               };
+       };
+};
+
+&ecspi2 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       can0: can@0 {
+               compatible = "microchip,mcp2518fd";
+               reg = <0>;
+               microchip,rx-int = <&gpio4 31 IRQ_TYPE_LEVEL_LOW>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_can0>;
+               interrupt-parent = <&gpio5>;
+               interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+               spi-max-frequency = <20000000>;
+               clocks = <&clk40m>;
+               status = "okay";
+       };
+};
+
+&iomuxc {
+       pinctrl_can0: can0grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0         0x00
+                       MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31       0x00
+               >;
+       };
+};

diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dts
new file mode 100644 (file)
index 0000000..fd7274e
--- /dev/null
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied-can1.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "imx8mm-pinfunc.h"
+
+&{/} {
+       clocks {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clk40m: clk@1 {
+                       compatible = "fixed-clock";
+                       reg = <1>;
+                       #clock-cells = <0>;
+                       clock-frequency = <40000000>;
+                       clock-output-names = "clk40m";
+               };
+       };
+};
+
+&ecspi3 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       can1: can@0 {
+               compatible = "microchip,mcp2518fd";
+               reg = <0>;
+               microchip,rx-int = <&gpio5 28 IRQ_TYPE_LEVEL_LOW>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_can1>;
+               interrupt-parent = <&gpio5>;
+               interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+               spi-max-frequency = <20000000>;
+               clocks = <&clk40m>;
+               status = "okay";
+       };
+};
+
+&iomuxc {
+       pinctrl_can1: can1grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29       0x00
+                       MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28       0x00
+               >;
+       };
+};

diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dts
new file mode 100644 (file)
index 0000000..06fa77c
--- /dev/null
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm0.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+&{/} {
+       regulatot-tpm0-rst {
+               compatible = "regulator-fixed";
+               regulator-name = "tpm0-rst";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+               regulator-always-on;
+               enable-active-high;
+       };
+};
+
+&ecspi2 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       tpm0: tpm@0 {
+               compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+               reg = <0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_tpm0>;
+               spi-max-frequency = <5000000>;
+               status = "okay";
+       };
+};
+
+&iomuxc {
+       pinctrl_tpm0: tpm0grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31       0x0
+               >;
+       };
+};

diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dts
new file mode 100644 (file)
index 0000000..c9676a3
--- /dev/null
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied-tpm1.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+&{/} {
+       regulator-tpm1-rst {
+               compatible = "regulator-fixed";
+               regulator-name = "tpm1-rst";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+               gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;
+               regulator-always-on;
+               enable-active-high;
+       };
+};
+
+&ecspi3 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       tpm1: tpm@0 {
+               compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+               reg = <0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_tpm1>;
+               spi-max-frequency = <5000000>;
+               status = "disabled";
+       };
+};
+
+&iomuxc {
+       pinctrl_tpm1: tpm1grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28       0x0
+               >;
+       };
+};

diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-ied.dts b/arch/arm/dts/imx8mm-cl-iot-gate-ied.dts
new file mode 100644 (file)
index 0000000..b854851
--- /dev/null
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-ied.dts
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Linaro
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mm-pinfunc.h"
+
+&ecspi1 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       fsl,spi-num-chipselects = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+       cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&ecspi2 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       fsl,spi-num-chipselects = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
+       cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&ecspi3 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       fsl,spi-num-chipselects = <1>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
+       cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
+       status = "okay";
+};
+
+&iomuxc {
+       pinctrl_ecspi1: ecspi1grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK    0x82
+                       MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI    0x82
+                       MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO    0x82
+               >;
+       };
+
+       pinctrl_ecspi1_cs: ecspi1cs {
+               fsl,pins = <
+                       MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9       0x40000
+               >;
+       };
+
+       pinctrl_ecspi2: ecspi2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK    0x02
+                       MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI    0x02
+                       MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO    0x102
+               >;
+       };
+
+       pinctrl_ecspi2_cs: ecspi2_csgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13      0x40000
+               >;
+       };
+
+       pinctrl_ecspi3: ecspi3grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK      0x02
+                       MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI      0x02
+                       MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO      0x102
+               >;
+       };
+
+       pinctrl_ecspi3_cs: ecspi3_csgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25       0x40000
+               >;
+       };
+};