drivers: pci: add map_bar support for Enhanced Allocation

Makes dm_pci_map_bar API available for integrated PCI devices that
support Enhanced Allocation instead of the original PCI BAR mechanism.

Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index cf1e7617ae3522599b1f0ca2b7ece743920af330..389aec15ce7b6ece8c0d608a0d9acf5454394b31 100644 (file)
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1341,10 +1341,56 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
        return bus_addr;
 }
 
+static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
+                              int ea_off)
+{
+       int ea_cnt, i, entry_size;
+       int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
+       u32 ea_entry;
+       phys_addr_t addr;
+
+       /* EA capability structure header */
+       dm_pci_read_config32(dev, ea_off, &ea_entry);
+       ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
+       ea_off += PCI_EA_FIRST_ENT;
+
+       for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
+               /* Entry header */
+               dm_pci_read_config32(dev, ea_off, &ea_entry);
+               entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
+
+               if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
+                       continue;
+
+               /* Base address, 1st DW */
+               dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
+               addr = ea_entry & PCI_EA_FIELD_MASK;
+               if (ea_entry & PCI_EA_IS_64) {
+                       /* Base address, 2nd DW, skip over 4B MaxOffset */
+                       dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
+                       addr |= ((u64)ea_entry) << 32;
+               }
+
+               /* size ignored for now */
+               return map_physmem(addr, flags, 0);
+       }
+
+       return 0;
+}
+
 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
 {
        pci_addr_t pci_bus_addr;
        u32 bar_response;
+       int ea_off;
+
+       /*
+        * if the function supports Enhanced Allocation use that instead of
+        * BARs
+        */
+       ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
+       if (ea_off)
+               return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
 
        /* read BAR address */
        dm_pci_read_config32(dev, bar, &bar_response);

diff --git a/include/pci.h b/include/pci.h
index 40c7751acf71837b141d097913bc14dc7c75ac17..0aab4381592867ecea2cb7ac78e8e6c52d878493 100644 (file)
--- a/include/pci.h
+++ b/include/pci.h
@@ -455,6 +455,17 @@
 #define PCI_EXT_CAP_ID_PTM     0x1F    /* Precision Time Measurement */
 #define PCI_EXT_CAP_ID_MAX     PCI_EXT_CAP_ID_PTM
 
+/* Enhanced Allocation Registers */
+#define PCI_EA_NUM_ENT         2       /* Number of Capability Entries */
+#define  PCI_EA_NUM_ENT_MASK   0x3f    /* Num Entries Mask */
+#define PCI_EA_FIRST_ENT       4       /* First EA Entry in List */
+#define  PCI_EA_ES             0x00000007 /* Entry Size */
+#define  PCI_EA_BEI            0x000000f0 /* BAR Equivalent Indicator */
+/* Base, MaxOffset registers */
+/* bit 0 is reserved */
+#define  PCI_EA_IS_64          0x00000002      /* 64-bit field flag */
+#define  PCI_EA_FIELD_MASK     0xfffffffc      /* For Base & Max Offset */
+
 /* Include the ID list */
 
 #include <pci_ids.h>
@@ -1312,6 +1323,8 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
  * that corresponds to it.
  * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
  * type 1 functions.
+ * Can also be used on type 0 functions that support Enhanced Allocation for
+ * 32b/64b BARs.  Note that duplicate BEI entries are not supported.
  *
  * @dev:       Device to check
  * @bar:       Bar register offset (PCI_BASE_ADDRESS_...)