mmc: zynq_sdhci: Fix SDx_BASECLK configuration

The DLL mode supported SD reference clocks are 50 MHz, 100 MHz and
200 MHz. When user select SD frequency as 200MHz in the design, the
actual frequency is going to come around ~187MHz (<= 200MHz considering
the parent clock and divisor selection). We need to set SDx_BASECLK as
200 in this case, setting 187 will result in tuning failures in mmc.

Set SDx_BASECLK to exact value of 200, 100 or 50 based on the frequency
range.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Link: https://lore.kernel.org/r/6c1e5eeeedd2864a0c85e6b409d182031d8c6c1a.1648210268.git.michal.simek@xilinx.com

diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index d96f5d543f545f8c147c5a8003fb32291104d06c..a59d96c6bdadf41b067d70e36cdc7ccb5abcc8d5 100644 (file)
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -765,6 +765,15 @@ static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv,
 
        mhz = DIV64_U64_ROUND_UP(clock, 1000000);
 
+       if (mhz > 100 && mhz <= 200)
+               mhz = 200;
+       else if (mhz > 50 && mhz <= 100)
+               mhz = 100;
+       else if (mhz > 25 && mhz <= 50)
+               mhz = 50;
+       else
+               mhz = 25;
+
        ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz);
        if (ret) {
                dev_err(dev, "SD_CONFIG_BASECLK failed\n");