clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC

clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC

Add the clock gate registers as well as the reset register bits for the
EMAC and EPHY for the V3s. These are needed by the sun8i network driver.

Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>