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riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL
authorYu Chien Peter Lin <peterlin@andestech.com>
Mon, 6 Feb 2023 08:10:49 +0000 (16:10 +0800)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Fri, 17 Feb 2023 11:07:48 +0000 (19:07 +0800)
commit600a708c0551cb31a7f4f553ec9347b0280cf21e
tree0974016a0055021ce694ff5785addaf3066602f0tree | snapshot
parentc1b88196807e1dd797aea6cc7ddb0dce02b4e898commit | diff
riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL

This patch refines L1 cache enable/disable and v5l2-cache enable
functions.

Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
arch/riscv/cpu/ax25/cache.c diff | blob | history
My U-Boot fork