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(parent: e8e3f2d) | patch
ARM: socfpga: fix data and tag latency values for pl310 cache controller
authorDinh Nguyen <dinguyen@kernel.org>
Sun, 3 Mar 2019 17:02:10 +0000 (11:02 -0600)
committerMarek Vasut <marex@denx.de>
Sat, 9 Mar 2019 16:59:13 +0000 (17:59 +0100)
commit532a54e65278564ac16878cda7146d247d8b3193
treea76dcbaa47389d90a8e704160517da3f8cb69653tree | snapshot
parente8e3f2d2d48f97b2c79b698eccedce8f4f880993commit | diff
ARM: socfpga: fix data and tag latency values for pl310 cache controller

The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
arch/arm/mach-socfpga/misc.c diff | blob | history
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